MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 258

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Direct Memory Access (DMA)
These settings generate the following sequence of events:
The DMA becomes idle or services the next channel.
9-38
1. First hardware (IPD_REQ) request for channel service.
2. The channel is selected by arbitration for servicing.
3. DMA_ENGINE writes: TCD.done = 0, TCD.start = 0, TCD.active = 1.
4. DMA_ENGINE reads: channel TCD data from local memory to internal register file.
5. The source to destination transfers are executed as follows:
6. DMA_ENGINE writes: TCD.SADDR = 0x1010, TCD.DADDR = 0x2010, TCD.CITER = 1.
7. DMA_ENGINE writes: TCD.ACTIVE = 0.
8. The channel retires → one iteration of the major loop.
9. Second hardware (IPD_REQ) requests channel service.
10. The channel is selected by arbitration for servicing.
11. DMA_ENGINE writes: TCD.DONE = 0, TCD.START = 0, TCD.ACTIVE = 1.
12. DMA_ENGINE reads: channel TCD data from local memory to internal register file,
13. The source to destination transfers are executed as follows:
TCD.citer =
TCD.slast = -32
TCD.dlast_sga= -32
a) READ_BYTE(0x1000), READ_BYTE(0x1001), READ_BYTE(0x1002),
b) WRITE_WORD(0x2000) → first iteration of the minor loop.
c) READ_BYTE(0x1004), READ_BYTE(0x1005), READ_BYTE(0x1006),
d) WRITE_WORD(0x2004) → second iteration of the minor loop.
e) READ_BYTE(0x1008), READ_BYTE(0x1009), READ_BYTE(0x100A),
f) WRITE_WORD(0x2008) → third iteration of the minor loop.
g) READ_BYTE(0x100C), READ_BYTE(0x100D), READ_BYTE(0x100E),
h) WRITE_WORD(0x200C) → last iteration of the minor loop.
a) READ_BYTE(0x1010), READ_BYTE(0x1011), READ_BYTE(0x1012),
b) WRITE_WORD(0x2010) → first iteration of the minor loop.
c) READ_BYTE(0x1014), READ_BYTE(0x1015), READ_BYTE(0x1016),
d) WRITE_WORD(0x2014) → second iteration of the minor loop.
e) READ_BYTE(0x1018), READ_BYTE(0x1019), READ_BYTE(0x101A),
f) WRITE_WORD(0x2018) → third iteration of the minor loop.
READ_BYTE(0x1003).
READ_BYTE(0x1007).
READ_BYTE(0x100B).
READ_BYTE(0x100F).
READ_BYTE(0x1013).
READ_BYTE(0x1017).
READ_BYTE(0x101B).
TCD.biter
MPC5125 Microcontroller Reference Manual, Rev. 2
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Freescale Semiconductor