MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 307

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.5.2
The DIU is initialized by correctly configuring its registers before enabling the DIU by setting the
DIU_MODE to a legal, non-zero value. The DIU supports as many as three planes, which are activated by
setting the corresponding DESC_n register to a non-zero value, and deactivated by setting the
corresponding DESC_n register to 0x0000_0000.
10.5.3
Three interrupt status bits are defined in the DIU for synchronization purpose. They are VSYNC,
LS_BF_VS, and VSYNC_WB.
If enabled, the VSYNC status bit is always asserted in the first cycle in which the VSYNC pulse is active.
With this interrupt the host can always observe the beginning of a new frame. Beside this, another
interrupt, LS_BF_VS (lines before vsync) can be used to set a deadline for the host to program the DIU
for the next frame. This interrupt is asserted at a user-specified number of lines (set by the LS_BF_VS
threshold,
Figure 10-51
the DIU. At the end of each frame the DIU starts processing the next frame by first loading the necessary
AD, palette, cursor, and gamma information from external memory pointed to by its internal register
values. All of this takes place in the time window marked by the two dotted blue lines in
host needs to make sure the proper data is in external memory and proper address values are programmed
into the DIU’s registers before this window. Reprogramming the palette, gamma, cursor, or AD pointers
in this time window is blocked. For this reason the host should use the LS_BF_VS interrupt to start setting
up the DIU for the next frame, while the LS_BF_VS threshold should be set to trigger the interrupt before
Freescale Semiconductor
4. Program DIU pixel clock divide ratio and turn on the clock in the system clock module. Enable
5. Program the DIU PLUT register and the DRAM controller priority manager as appropriate so that
6. Prepare the palette, gamma tables, and cursor bitmap in memory (DDR DRAM) and set the
7. Prepare the area descriptors in memory (DDR DRAM) and set the pointers to them. This step is
8. Program the INT_MASK register and enable the interrupts needed for the application (by default,
9. Configure the WB_MEM_ADDR register if the operating mode is mode 2 or 3.
10. Set the operating mode (by configuring the DIU_MODE register) to turn on the DIU.
pixel clock inversion or the programmable pixel clock delay if necessary so that the interface AC
timing requirement can be met.
the DIU priority can be escalated dynamically, to make sure no buffer underrun would be hit.
pointers to them. This step is not strictly required because the user might be using it in an
application without palette, gamma, or cursor. However, it is recommended to load zero contents
in this case so that the internal SRAM can be initialized. The gamma table is always in use except
in mode 3.
also not strictly required because the default background colors can be displayed or a mode that
does not require area descriptors (mode 4) may be selected.
all interrupts are disabled after hardware reset).
Figure
Controlling DIU Planes after the DIU is Enabled
Synchronizing with the Host (CPU)
shows a timing diagram on how these two interrupts can be used to synchronize the host and
10-17) before the vertical front porch (FP_V).
MPC5125 Microcontroller Reference Manual, Rev. 2
Display Interface Unit (DIU)
Figure
10-51. The
10-45