MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 193

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.4.8.2
This basic IFR receiving flow can be interrupted for the same reasons as a normal message reception. The
IFR receiving process can be adversely affected due to a CRC error, an Invalid or Out of Range Symbol
or due to a receiver overrun caused by the CPU failing to service an RxIFR interrupt in a timely fashion.
For a description of how these exceptions can affect the IFR receiving process, refer to
“Receiving Exceptions.”
6.4.9
There are a few special operations that the BDLC module can perform. What follows is a brief description
of each of these functions and when they might be used.
6.4.9.1
The BDLC module, because it handles each message on a byte-by-byte basis, has the inherent capability
of handling messages any number of bytes in length. While during normal operation this requires the user
to carefully monitor message lengths to ensure compliance with SAE J1850 message limits, often in a
production or diagnostic environment messages that exceed the SAE J1850 limits can be beneficial. This
is especially true when large amounts of configuration data need to be downloaded over the SAE J1850
network.
Because of the BDLC module’s architecture, it can both transmit and receive messages of unlimited
length. The CRC calculations for transmitting and receiving are not limited to eight bytes, but are instead
calculated and verified using all bytes in the message, regardless of the number. All control bits, including
TEOD and IMSG, also work in an identical manner, regardless of the length of the message.
To transmit or receive these block mode messages, no extra BDLC module control functions must be
performed. The user simply transmits or receives as many bytes as desired in one message frame, and the
BDLC module operates as if a message of normal length was being used.
Freescale Semiconductor
whether or not the last byte of the IFR is a CRC byte, and if so verify that the CRC byte is correct.
If the CRC byte is not correct, this is reflected in the BDLC_DLCBSVR register.
After an additional period of time, the EOD symbol transitions into an EOF symbol. When the EOF
is received, it is reflected in BDLC_DLCBSVR, indicating to the user that the IFR and the message
is complete.
Special BDLC Module Operations
Receiving IFR Exceptions
Transmitting Or Receiving A Block Mode Message
MPC5125 Microcontroller Reference Manual, Rev. 2
Byte Data Link Controller (BDLC)
Section 6.4.6.4,
6-57