MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 571

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
An ALE signal is asserted during this address tenure. ALE level is programmable to be low or high. The
dedicated R/W output is also driven with ALE (and throughout the cycle). One clock after the ALE
negates, the appropriate CS pin asserts (low) and the AD bus enters the data tenure (isolation cycle). The
CS pin and this data tenure remain active until the programmed wait states expire or the device responds
with an ACK assertion. ACK polarity is active low, but can be programmed to be ignored. The data tenure
can contain up to the full 32-bit width. However, the data width is programmable to support dynamic
bus-sized transactions.
The muxed mode requires external logic to latch the address during the address tenure and to decode bank
selects if they are encoded. This mode is slower than the non-muxed mode because data and address are
muxed in time. The supported address space is limited by the 30 address lines. In muxed mode, the LPC
can access as much as 4 GB of data.
21.3.2.1
The address is presented on the corresponding AD bus bits, which total 32 bits (AD[31:0]).
The TSIZ bits appear on AX[34] (TSIZ most significant bit) to AX[33] (TSIZ least significant bit). These
bits are calculated and driven by the LPC based on the internal byte lane enables on the IP bus.
TSIZ [1:0] are driven as follows:
Freescale Semiconductor
AD[29:24]
AD[23:16]
AD[15:8]
AD[7:0]
Signal
AD[31]
AD[30]
Name
ALE represents the programmable value of the ALE bit (csboot/csx configuration registers).
Table 21-30. Internal Data and Address Bus Assignment to External Signals in Muxed Mode
01 = Transaction is 1 byte
10 = Transaction is 2 bytes
00 = Transaction is 4 bytes
address 31 address 31
address 30 address 30
address
address
address
address
Address Tenure
[29:24]
[23:16]
Phase
[15:8]
Addr
[7:0]
8-Bit Data Bus
Isolation
address
address
address
address
[29:24]
[23:16]
[15:8]
[7:0]
Only TSIZes of one, two, or four are supported.
MPC5125 Microcontroller Reference Manual, Rev. 2
(Short/Word Addressing) (continued)
Phase
Data
data
[7:0]
0
0
0
0
0
address 31 address 31
address
address
address
address
[30:25]
[24:17]
Phase
[16:9]
Addr
[8:1]
0
NOTE
16-Bit Data Bus
Isolation
address
address
address
address
[30:25]
[24:17]
[16:9]
[8:1]
0
Phase
[15:8]
Data
data
data
[7:0]
0
0
0
0
address
address
address
address
[31:26]
[25:18]
[17:10]
Phase
Addr
[9:2]
0
0
LocalPlus Bus Controller (LPC)
32-Bit Data Bus
Isolation
address
address
address
address
[31:26]
[25:18]
[17:10]
[9:2]
0
0
[29:24]
[23:16]
Phase
[15:8]
Data
D31
D30
data
data
data
data
[7:0]
21-31