MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 622

IC MCU 32BIT E300 324TEPBGA

MPC5125YVN400

Manufacturer Part Number
MPC5125YVN400
Description
IC MCU 32BIT E300 324TEPBGA
Manufacturer
Freescale Semiconductor
Series
MPC51xxr

Specifications of MPC5125YVN400

Core Processor
e300
Core Size
32-Bit
Speed
400MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, USB OTG
Peripherals
DMA, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.33 V ~ 1.47 V
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
324-PBGA
Processor Series
MPC51xx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
Maximum Clock Frequency
400 MHz
Operating Supply Voltage
1.4 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
3.3 V
Interface Type
CAN, I2C
Minimum Operating Temperature
- 40 C
Program Memory Size
32 bit
Cpu Speed
400MHz
Embedded Interface Type
CAN, I2C, SPI, UART, USB
Digital Ic Case Style
TEPBGA
No. Of Pins
324
Rohs Compliant
Yes
Cpu Family
MPC5xx
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
32KB
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC5125YVN400
Manufacturer:
Freescale Semiconductor
Quantity:
135
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Manufacturer:
LTC
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Part Number:
MPC5125YVN400
Manufacturer:
Freescale Semiconductor
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MSCAN
The synchronization jump width
parameter.
The above parameters are set by programming the MSCAN Bus Timing Registers (CANBTR0,
CANBTR1) (see
“MSCAN Bus Timing Register 1
Table 22-32
22.4.6
The MSCAN generates an internal time stamp when a valid frame is received or transmitted and the TIME
bit is enabled. Because the CAN specification defines a frame to be valid if no errors occur before the End
of Frame (EOF) field is transmitted successfully, the actual value of an internal timer is written at EOF to
the appropriate time stamp position within the transmit buffer. For receive frames, the time stamp is written
to the receive buffer.
1. Reference the Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing.
22-44
Time Segment 1
Transmit Point
Sample Point
SYNC_SEG
Timer Link
gives an overview of the CAN compliant segment settings and the related parameter values.
Syntax
5 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
9 .. 16
Ensure the bit time settings are in compliance with the CAN standard.
Section 22.3.2.1, “MSCAN Control 0 Register (CANCTL0),”
Table 22-32. CAN Standard Compliant Bit Time Segment Settings
System expects transitions to occur on the bus during this period.
A node in transmit mode transfers a new value to the CAN bus at this point.
A node in receive mode samples the bus at this point. If the three samples per bit option
is selected, this point marks the position of the third sample.
TSEG1
3 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
4 .. 9
MPC5125 Microcontroller Reference Manual, Rev. 2
1
(CANBTR1)”).
can be programmed in a range of 1 to 4 time quanta by setting the SJW
Table 22-31. Time Segment Syntax
Time Segment 2
2
3
4
5
6
7
8
NOTE
Description
TSEG2
1
2
3
4
5
6
7
Synchronization
Jump Width
1 .. 2
1 .. 3
1 .. 4
1 .. 4
1 .. 4
1 .. 4
1 .. 4
and
Freescale Semiconductor
Section 22.3.2.4,
0 .. 1
0 .. 2
0 .. 3
0 .. 3
0 .. 3
0 .. 3
0 .. 3
SJW

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