MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 279

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.3.3.16 Synchronization Signals Polarity Register (SYN_POL)
The Synchronization Signals Polarity Register (SYN_POL) selects polarity for the horizontal sync
(HSYNC), vertical sync (VSYNC), and composite sync (CSYNC) synchronization signals, and controls
bypassing the HSYNC or VSYNC signals with the CSYNC signal.
Freescale Semiconductor
Address: Base + 0x3C
Reset
Reset
INV_CS
INV_HS
INV_VS
BP_VS
BP_HS
PW_V
BP_V
FP_V
Field
Field
W
W
R
R
16
0
0
0
0
0
VSYNC back-porch pulse width (in HSYNC signal cycles) It can be 0.
VSYNC active pulse width (in HSYNC signal cycles).
Note: This bit must be set to a non-zero value for the display to operate.
VSYNC front-porch pulse width (in HSYNC signal cycles). It can be 0.
Bypass Vertical Synchronize Signal (internal pin muxing)
0 Do not bypass the VSYNC signal output.
1 CSYNC bypasses the VSYNC signal and outputs CSYNC instead of VSYNC.
Bypass Horizontal Synchronize Signal (internal pin muxing)
0 Do not bypass the HSYNC signal output.
1 CSYNC bypasses the HSYNC signal, and outputs CSYNC instead of HSYNC.
Invert Composite Synchronize Signal
0 CSYNC signal is not inverted and is active HIGH.
1 CSYNC signal is inverted and is active LOW.
Invert Vertical Synchronize Signal
0 VSYNC signal is not inverted and is active HIGH.
1 VSYNC signal is inverted and is active LOW.
Invert Horizontal Synchronize Signal
0 HSYNC signal is not inverted and is active HIGH.
1 HSYNC signal is inverted and is active LOW.
17
0
0
0
0
1
Figure 10-16. Synchronization Signals Polarity Register (SYN_POL)
18
0
0
0
0
2
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 10-18. VSYN_PARA field descriptions
Table 10-19. SYN_POL field descriptions
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
Description
24
8
0
0
0
0
25
9
0
0
0
0
10
26
0
0
0
0
BP_
VS
11
27
0
0
0
BP_
HS
12
28
0
0
0
Display Interface Unit (DIU)
Access: User read/write
INV_
CS
13
29
0
0
0
INV_
VS
14
30
0
0
0
INV_
10-17
HS
15
31
0
0
0