MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 299

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

transparent) to 255 (pixel is completely opaque). The following equation represents the transfer function
of the blending operation including the alpha values. No alpha component is defined for plane 1, because
it has no planes behind it.
For mode 2, when only planes 2 and 3 are blended to write back, the equation changes to:
10.4.6
For each area (see
minimum value for the chroma keying function. The maximum and minimum values are specified as R,
G, and B values to which every pixel in the bitmap is compared. If all the components are greater or equal
to the minimum and less than or equal to the maximum, then the alpha component for that particular pixel
is replaced with 0. The chroma keying operation is performed after the color format conversion with all
the components extended to 8 bits.
To turn the chroma keying off, set the minimum to 255 and the max to 0 for each component. To produce
a green-screen type of effect in which all green pixels (0,255,0) are to be turned transparent, the maximum
and minimum should both be set to (0,255,0).
10.4.7
The gamma table allows the user to define a completely arbitrary transfer function at the output of each
color component. The gamma table should be created in memory as a consecutive sequence of 256 bytes
for each color component accessed by the hardware as an indexed matrix so that
output_color_component = gamma_table[input_color_component].
All three gamma tables must be stored in memory (DDR DRAM) consecutively beginning with red, then
green, and blue at the end.
Similar to the palette, the gamma table is also automatically loaded by the DIU from memory into an
embedded SRAM before it starts on processing the next frame if the CPU writes to the GAMMA register
(see
The size of the SRAM is 3 × 256 bytes, but it is organized as 96 × 64 bits. So the address range for each
color component table is:
Freescale Semiconductor
•
•
•
Section 10.3.3.4, “Gamma Table Pointer Register
out_pixel=
Gamma_red: 0x0~0x0FF
Gamma_green: 0x100~0x1FF
Gamma_blue: 0x200~0x2FF
Chroma Keying
Gamma Correction
pixel_1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -
Section 10.4.1, “Area
×
(
255 α 2
writeback
MPC5125 Microcontroller Reference Manual, Rev. 2
–
)
×
(
=
255 α 3
Descriptor”), the user needs to specify a maximum and a
plane2
--------------------------------------------------------------------------------------- -
–
)
×
+
(
pixel_2
255 α 3
(GAMMA)”).
255 2
–
255
×
)
α 2
+
plane3
×
(
255 α 3
×
–
α 3
)
+
pixel_3
Display Interface Unit (DIU)
×
255 α 3
×
Eqn. 10-1
Eqn. 10-2
10-37