MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 352

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Multi-port DRAM Controller Priority Manager
The shift register shifts in information of the recent ACKs. This 63-stage shift register contains
information on the last 63 bus cycles of the DRAM controller.
The shift register is shifted any time a read or write request has been granted to the DRAM (An ACK to
the requesting bus) or when there is an IDLE_PULSE. An idle pulse is generated every time the DRAM
is idle for four consecutive clock cycles. Idle means none of the five incoming buses is making a request.
The shift data in is the corrected ACK for the self channel. If the shift register shifts because the current
cycle is granted to the self channel, a 1 is shifted in, if not a 0 is shifted in. It always occurs like this when
the own channel is requesting access. However, if the own channel is not requesting access, depending on
control bit ACK_SEL, a 1 or a 0 is shifted in. If ACK_SEL is 1, a 1 is shifted in all the time when the self
channel is not requesting and there is an ACK on any other channel or an idle pulse. If ACK_SEL is 0,
zeros are shifted in.
The correction for the non-requesting channel allows you to steer the default priority, the priority that the
channel gets, when it has not been requesting for some time. If ACK_SEL is set 1, the default priority is
low. This setting is appropriate for peripherals with (large) FIFOs. When they are not requesting, the FIFO
is quite full. When they do get on the bus, they can start with low priority and escalate to higher after some
time.
Setting ACK_SEL to 0 is appropriate for peripherals that desire high priority. In this case, the Power
Architecture processor should receive high priority. When it is not on the bus, it is because it finds the
instruction or data that it needs in the processor caches, so it does not request. When the cache misses, the
request comes on the bus, and needs to be serviced fast. Therefore, ACK_SEL is set to 0, the default
priority is high and servicing fast. If the Power Architecture Processor gets on the bus a lot (due to a lot of
cache swapping), the priority manager detects this and degrades its priorities over time. The other masters
continue to receive their fair share of bus bandwidth.
The output of the shift register is ANDED in to look at only the last n ACKs. Logic decodes the ANDing
code from the ACK_COUNT bitfield. The number of ones after the ANDing is added up in ADDER 4 and
saturated. The result out of ADDER 4 is a number from 0 to 15. This number is input in the look-up table.
Table look-up content is taken for channel 1 from register lut table 1 main[63:0] or lut table 1
12-20
20
21
Read or write on
any channel OR
idle pulse
Own channel
serviced OR
Own channel not
requesting
22
ack_count
Data
in
en
63-bit
1
Combinatorial
Logic
2
3
23
DIU_priority[3]
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 12-18. Priority Channel Block Diagram
24
congested
4
7
0
1
Look-up
Table
5
0
1
28
6
alternate look-up table
main look-up table
LUT sel
DIU priority[3:0]
25
8
D
ONLY DIU channel
26
27
1
0
9
DIU overrule
chan_priority[3:0]
29
30
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