MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 402

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
The hash table algorithm used in the group and individual hash filtering operates as follows. The 48-bit
destination address is mapped into one of 64 bits, which are represented by 64 bits stored in
ETH_GADDR1/ETH_GADDR2 (group address hash match) or ETH_IADDR1/ETH_IADDR2
(individual address hash match). This mapping is performed by passing the 48-bit address through the
on-chip 32-bit CRC generator and selecting the 6 most significant bits of the CRC-encoded result to
generate a number between 0 and 63. The MSB of the CRC result selects ETH_GADDR1 (MSB = 1) or
ETH_GADDR2 (MSB = 0). The least significant 5 bits of the hash result select the bit within the selected
register. If the CRC generator selects a bit set in the hash table, the frame is accepted. Otherwise, it is
rejected.
For example, if eight group addresses are stored in the hash table and random group addresses are received,
the hash table prevents roughly 56/64 (or 87.5%) of the group address frames from reaching memory.
Those that do reach memory must be further filtered by the processor to determine if they truly contain
one of the eight desired addresses.
The effectiveness of the hash table declines as the number of addresses increases.
The hash table registers must be initialized. The FEC does not support the set group address command,
which can be used in the CPM ethernet controllers. You may compute the hash for a particular address in
14-46
NOTES:
FCE — field in ETH_R_CNTRL register (Flow Control Enable)
I/G — Individual/Group bit in Destination Address (least significant bit in first byte received in MAC frame)
False
Reject Frame
Flush from FIFO
Hash Search
Group Table
False
FCE
Match
Figure 14-31. Ethernet Address Recognition — Microcode Decisions
?
?
False
True
True
Receive Frame
MPC5125 Microcontroller Reference Manual, Rev. 2
Pause Address
?
Group
True
Receive Frame
Receive Address
Recognition
I/G Address
Receive Frame
?
True
Individual Table
False
Individual
Hash Search
Flush from FIFO
Reject Frame
Match
?
False
Exact Match
?
Freescale Semiconductor
Receive Frame
True