MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 287

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Display Interface Unit (DIU)
10.4
Functional Description
The DIU does not have internal frame buffers. It reads the data from the main memory (DDR DRAM) at
the same rate it refreshes the display.
Besides generating all the signals required to drive the display, the DIU manages real time blending of as
many as three planes onto the display. Alpha blending is performed between the planes. Chroma key
support is also present to help relieve the host processor from all the computational and bandwidth
consuming blending tasks while simultaneously allowing the users to maintain the graphics quality
required by many applications.
WELCOME
TO AUSTIN
Plane 1
Display
Plane 2
WELCOME
TO AUSTIN
Plane 3
Figure 10-31. Three Plane Blending
10.4.1
Area Descriptor
The area descriptor (AD) defines each area to be displayed on a plane. A plane can display more than one
area as long as the areas do not share a scan line.
The areas (for a plane) must be sorted in vertical order from top to bottom. The area descriptor is set up in
the system’s main memory (DDR DRAM) and then retrieved by the DIU directly from there.
Change the displayed data between frames by changing the data in the current area descriptor or create a
new one and change the pointer in the DIU while keeping the previous one for future use or reference. It
is always assumed that the bitmaps are stored pixel by pixel in memory, starting from the top-left most
pixel in the image and continued sequentially until the last pixel (the bottom-right most pixel) by scanning
the image always from left to right and top to bottom.
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
10-25