MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 105

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.2.7
The clock system provides a logic to observe the System PLL output frequency. A deviation of more than
1% of the target frequency of the PLL output clock (spll_out) will be indicated as unlock. The time
between the PORESET and the first lock event will be stored in the SYSPLL_LOCK_CNT register. For
more information, see
5.2.8
5.2.8.1
The output of the system PLL conforms to the following equation:
Freescale Semiconductor
System PLL lock detection
System PLL and e300 PLL
System PLL Programming Model
Section 5.3.1.28, “System PLL Lock Counter Register (SPLL_LOCK_CNT).”
MPC5125 Microcontroller Reference Manual, Rev. 2
MPC5125
Figure 5-5. RTC Clock Generation
f
spll
= SPMF × f
Generation
V
System
Clock
BAT
Domain
RTC Module
ref_clk
V
CORE
Domain
ips_clk
Clocks and Low-Power Modes
Eqn. 5-1
5-5