MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 857

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.2.4.8
The Current Asynchronous List Address Register (USB_ASYNCLISTADDR) contains the address of the
next asynchronous queue head to be executed by the host. Bits [4:0] of this register cannot be modified by
the system software and always return 0s when read.
On the OTG module, this register is shared between the host and device mode functions. In host mode, it
is the USB_ASYNCLISTADDR register; in device mode, it is the USB_ENDPOINTLISTADDR register.
See
more information.
Freescale Semiconductor
Address: Base + 0x158
USBADRA
ASYBASE
Reset
Reset
USBADR
Section 32.2.4.9, “Endpoint List Address (USB_ENDPOINTLISTADDR) Register (Non-EHCI),”
Field
Field
W
W
R
R
16
Figure 32-22. Current Asynchronous List Address Register (USB_ASYNCLISTADDR)
0
0
0
Current Asynchronous List Address Register (USB_ASYNCLISTADDR)
Device Address. This field corresponds to the USB device address.
Device Address Advance. Default = 00. When this bit is 0, any writes to USBADR are instantaneous. When
this bit is written to a 1 at the same time or before USBADR is written, the write to the USBADR field is staged
and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR is loaded from the
holding register.
Hardware automatically clears this bit on the following conditions:
01)IN is ACKed to endpoint 0. (USBADR is updated from staging register).
10)OUT/SETUP occur to endpoint 0. (USBADR is not updated).
11)Device Reset occurs (USBADR is reset to 0).
Note: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR
Link Pointer Low (LPL). These bits correspond to memory address signal [31:5]. This field may only reference
a queue head (QH). Only used by the host controller.
17
0
0
1
field. This mechanism ensures this specification is met when the DCD cannot write to the device
address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with
USBADRA equaling 1 after the SET_ADDRESS data phase (before the prime of the status phase), the
USBADR is programmed instantly at the correct time and meets the 2 ms USB requirement.
18
0
0
2
Table 32-23. USB_ASYNCLISTADDR field descriptions
Table 32-22. USB_DEVICEADDR field descriptions
19
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
ASYBASE (cont.)
20
4
0
0
21
0
0
5
22
0
0
6
ASYBASE
23
0
0
7
Description
Description
24
8
0
0
25
9
0
0
Universal Serial Bus Interface with On-The-Go
10
26
0
0
11
27
0
0
0
12
28
0
0
0
Access: User read/write
13
29
0
0
0
14
30
0
0
0
32-29
15
31
0
0
0
for