MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 515

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.5
In master transmit mode, a data transfer is initiated when data is written to the DATA register. The most
significant bit is sent first.
In master receive mode, reading this register initiates next byte data receiving.
In slave mode, the same functions are available after an address match occurs. Data transfer is initiated by:
or
The I
interrupt enable bit is set, the I
The interrupt bit sets when one of the following events occurs:
19.5.1
In the interrupt service routine, software must clear the IF status bit first. The CF status bit is cleared
automatically by reading from the data I/O register (I2C_MDRn) in receive mode or writing to
I2C_MDRn in transmit mode.
Software may service the bus I/O in the main program by monitoring the IF status bit if the interrupt
function is disabled. Polling should monitor the IF status bit rather than the CF bit because its operation is
different when arbitration is lost.
When an interrupt occurs at the end of the address cycle, the master is always in transmit mode, i.e. the
address is transmitted. If master receive mode is required, indicated by R/W bit in the DATA register, the
TX control bit should be toggled at this stage.
During slave mode address cycles (AAS = 1), the SRW bit in the STATUS register is read to determine the
direction of the subsequent transfer and the TX control bit is programmed accordingly. The SRW bit is not
valid for data cycles (AAS = 0) when operating in slave mode. Therefore, the TX bit in the control register
should be read to determine the direction of the current transfer.
19.5.2
In the slave interrupt service routine, the AAS bit should be tested to determine if a calling of its own
address was received. If AAS is set, software should set the Tx/Rx mode select bit (control register Tx
bit) according to the R/
AAS. The slave interrupt service routine should also move the data, depending on whether it acts as a
transmitter or a receiver, as follows:
Freescale Semiconductor
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•
•
•
•
2
C interrupt STATUS register bit is set when an interrupt is pending. If the CONTROL register
Writing to the DATA register for slave transmits
A dummy reading from the DATA register in slave receive mode occurs.
A complete 1-Byte transfer (set at falling edge of ninth clock) occurs.
A receive calling address matches its own specific address in slave receive mode.
Arbitration is lost.
Transfer Initiation and Interrupt
Post-Transfer Software Response
Slave Mode
W
command bit (SRW). Writing to the CONTROL register automatically clears
2
MPC5125 Microcontroller Reference Manual, Rev. 2
C interrupt STATUS register bit, if set, causes a processor interrupt request.
Inter-Integrated Circuit (I
19-23
2
C)