MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 136

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clocks and Low-Power Modes
5-36
SYSPLL_LOCK
SYSPLL_LOCK The SYSPLL_LOCK captures the first lock event after HRESET. This bit is cleared by HRESET.
SYSPLL_LOCK
_UNLOCK
_STATUS
SYSPLL
_CNT
Field
The SYSPLL_LOCK_STATUS shows the current status of the system PLL lock detector.
0 System PLL is unlocked.
1 System PLL is locked.
The SYSPLL_UNLOCK captures the first unlock event after a lock event. This bit is cleared by HRESET.
0 No unlock event has occurred after the last lock event.
1 An unlock event has occurred after the last lock event.
0 No lock event occurred.
1 A lock event occurred.
The register contains the number of REF_CLK cycles between the PORESET deassertion and the System
PLL lock detector indicating the first time a lock state. (SYSPLL_LOCK = 1). This bitfield is cleared by
HRESET.
Note: The reset value of this bitfield is indeterminate.
Table 5-33. SPLL_LOCK_CNT field descriptions
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
Freescale Semiconductor