MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 95

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
4.6.1
The Reset Configuration Word Low register is shown in
according to the reset configuration word low loaded during the reset flow.
1
4.6.2
The Reset Configuration Word High register is shown in
according to the reset configuration word high loaded during the reset flow.
Freescale Semiconductor
Address: Base + 0x00
Default absolute offset with IMMRBAR at default location of 0xFF40_0000. See
Map (XLBMEN + Mem Map).”
In this column, the symbol “U” indicates one or more bits in a byte are undefined at reset. See the associated description for
more information.
See
Reset
Reset
SYSDIV
CPMF
SPMF
Field
Table
W
W
R
R
4-2. for more information.
16
0
0
0
0
0
Reset Configuration Word Low (RCWL) Register
Reset Configuration Word High (RCWH) Register
System PLL multiplication factor. See
Core PLL configuration. See
System clock divide factor. See
17
0
0
0
0
1
18
0
0
0
0
2
Figure 4-2. Reset Configuration Word Low (RCWL) Register
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
AD11
EMB_
20
4
0
0
Table 4-8. RCWL field descriptions
1
AD10
AD14
EMB_
EMB_
Section 5.2.8.2, “e300 Core PLL Programming Model.”
21
5
Section 5.3.1.5, “System Clock Frequency Register 2 (SCFR2).”
SPMF
1
1
SYSDIV
AD13
EMB_
EMB_
AD9
Section 5.2.8.1, “System PLL Programming Model.”
22
6
1
1
AD12
EMB_
EMB_
AD8
23
7
Description
1
1
Figure
Figure
24
8
0
0
0
0
4-2. This read-only register gets its value
4-3. This read-only register gets its value
25
9
0
0
0
0
Chapter 2, “System Configuration and Memory
10
26
0
0
0
0
11
27
0
0
0
0
12
28
0
0
0
0
Access: User read-only
EMB_
AD7
13
29
0
0
1
CPMF
EMB_
AD6
14
30
0
0
1
EMB_
AD5
Reset
15
31
0
0
4-9
1