MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 160

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Byte Data Link Controller (BDLC)
This clock resolution of 1 t
bits and symbols, without reducing the valid window for receiving bits and symbols from transmitters onto
the J1850 bus having varying oscillator frequencies.
6.4.2.10.1
Table 6-16
for the BDLC module. The units used in these tables are MUX interface clock periods (t
interface clock is a divided down version of the bus clock input to the module (see
Rate Select Register
counters that control symbol generation and identification. The symbol timing in effect during J1850
operations depends on the state of two control bits: the CLKS bit in the BDLC_DLCBCR1 register, which
indicates whether the bus clock is an integer frequency or a binary frequency; the 4XE bit in BDLC
Control Register 2, which is used to select 4X operation.
Table 6-16 andTable 6-18
and 4X operation disabled (4XE = 0). It is assumed that for integer bus frequencies the divided down
MUX interface clock frequency is 1 MHz (t
Table 6-17
(CLKS = 1) and 4X operation disabled (4XE = 0). It is assumed that the divided down MUX interface
clock frequency is 1.048576 MHz (t
values are adjusted to compensate for the shortening of the MUX interface clock period.
Table 6-20
enabled (4XE = 1) for both integer bus frequencies (CLKS = 0) and binary bus frequencies (CLKS = 1),
respectively.
The values specified in the tables are for the symbols appearing on the SAE J1850 bus. These values
assume the BDLC module is communicating on the SAE J1850 bus using an external analog transceiver,
and that the BDLC module analog round-trip delay value programmed into the BDLC_DLCBARD
register is the appropriate value for the transceiver being used. If these conditions are not met, the symbol
timings being measured on the SAE J1850 bus are significantly affected. For a detailed description of how
symbol timings are measured on the SAE J1850 bus, refer to the appropriate SAE documents.
6-24
Note: The transmitter timing for this symbol depends upon the minimum detection time of the symbol by the receiver.
Number
1
2
3
4
5
6
7
8
through
and
and
Transmit and Receive Symbol Timing Specifications
Table 6-21
Table 6-19
Table 6-16. BDLC Transmitter VPW Symbol Timing for Integer Frequencies
Inter-Frame Separator (IFS)
Table 6-21
(BDLC_DLCBRSR)”). The MUX interface clock drives the transmit and receive
End of Frame (EOF)
Start of Frame (SOF)
End of Data (EOD)
Passive Logic 0
Passive Logic 1
Characteristic
Active Logic 0
Active Logic 1
indicate the transmit and receive timing for integer bus frequencies (CLKS = 0)
show how the receive symbol timing values are adjusted when 4X operation is
bdlc
indicated the transmit and receive timing for binary bus frequencies
MPC5125 Microcontroller Reference Manual, Rev. 2
allows the BDLC module to properly differentiate between the different
contain the SAE J1850 transmit and receive symbol timing specifications
bdlc
1
1
= 0.953674 0 µs) for binary bus frequencies. The symbol timing
1
bdlc
= 10 µs).
Symbol
T
T
T
T
T
T
T
T
tvp1
tvp2
tva1
tva2
tva3
tvp3
tv4
tv5
Min
126
126
198
162
238
298
62
62
Typ
128
128
200
164
240
300
64
64
Section 6.3.2.6, “BDLC
Freescale Semiconductor
Max
130
130
202
166
242
302
66
66
bdlc
). The MUX
Unit
t
t
t
t
t
t
t
t
bdlc
bdlc
bdlc
bdlc
bdlc
bdlc
bdlc
bdlc