MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 377

IC MCU 32BIT E300 324TEPBGA

MPC5125YVN400

Manufacturer Part Number
MPC5125YVN400
Description
IC MCU 32BIT E300 324TEPBGA
Manufacturer
Freescale Semiconductor
Series
MPC51xxr

Specifications of MPC5125YVN400

Core Processor
e300
Core Size
32-Bit
Speed
400MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, USB OTG
Peripherals
DMA, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.33 V ~ 1.47 V
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
324-PBGA
Processor Series
MPC51xx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
Maximum Clock Frequency
400 MHz
Operating Supply Voltage
1.4 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
3.3 V
Interface Type
CAN, I2C
Minimum Operating Temperature
- 40 C
Program Memory Size
32 bit
Cpu Speed
400MHz
Embedded Interface Type
CAN, I2C, SPI, UART, USB
Digital Ic Case Style
TEPBGA
No. Of Pins
324
Rohs Compliant
Yes
Cpu Family
MPC5xx
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
32KB
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Freescale Semiconductor
Address: Base + 0x084
RMII_MODE RMII Mode. Indicates if the FEC is in RMII or MII/7-wire mode.
RMII_ECHO RMII Echo. Enables RMII echo mode. RMII 2-bit receive data is processed through the RMII receive logic to the
RMII_LOOP
RMII_10T
MAX_FL
Reset
Reset
Field
W
W
R
R
16
0
0
0
0
0
Maximum frame length. This is a user read/write field that resets to 0x5EE (decimal 1518). Length is measured
starting at DA (destination address) and includes the CRC at the end of the frame. Transmit frames longer than
MAX_FL causes a BABT interrupt to occur. Receive frames longer than MAX_FL cause a BABR interrupt to
occur and set the LG bit in the end-of-frame buffer descriptor. The recommended values to be programmed are
1518 (the default) or 1522 (if VLAN tags are supported).
FEC and also routes through the RMII’s transmit logic to become RMII 2-bit transmit data out.
0 Normal operation
1 RMII echo mode enabled.
Note: When RMII_ECHO is set, proper operation is guaranteed only when RMII_MODE = 1, RMII_LOOP = 0
RMII loopback. Enables RMII loopback mode. Causes the MII transmit outputs from the Ethernet controller to
loop back to the Ethernet controllers’s MII receive inputs through the RMII transmit/receive logic.
0 Normal operation
1 RMII loopback mode enabled.
Note: When RMII_LOOP is set, proper operation is guaranteed only when RMII_MODE = 1, RMII_ECHO = 0,
RMII 10-Base. Enables 10 Mbit/s mode of the RMII. Determines the clock frequency of the clock source to the
FEC logic to support 10/100Mbit/s operations.
0 100 Mbit/s operation. The 50 Mhz RMII reference clock on FECn_TX_CLK is sent to the RMII, while a
1 10Mbit/s operation. The 50MHz RMII reference clock on FECn_TX_CLK is divided by 10 (5 MHz) and sent
0 FEC configured for MII or 7-wire mode as indicated by the MII_MODE bit.
1 FEC configured for RMII operation, only if the MII_MODE bit is set.
The following table shows the valid settings for RMII_MODE and MII_MODE.
divided-by-2 version (25 MHz) is sent to the FEC.
to the RMII, while a divided-by-20 version (2.5 MHz) is sent to the FEC MII part.
17
0
0
0
0
1
and LOOP = 0.
LOOP =0, and ETH_X_CNTRL[FDEN] = 1.
18
0
0
0
0
2
Figure 14-11. Receive Control (ETH_R_CNTRL) Register
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 14-15. ETH_R_CNTRL field descriptions
ECHO
RMII_
20
4
0
0
0
MII_MODE RMII_MODE
RMII_
LOOP
21
1
0
5
1
1
0
RMII_
10T
22
0
0
6
MODE
RMII_
23
1
0
7
0
1
0
Description
24
8
1
0
0
25
9
1
0
0
Description
RMII mode
MII mode
MAX_FL
7-wire
FCE
10
26
1
0
BC_
REJ
11
27
0
0
Fast Ethernet Controller (FEC)
PROM
12
28
1
0
Access: User read/write
MODE
MII_
13
29
1
0
DRT LOOP
14
30
1
0
14-21
15
31
0
1

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