MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 443

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.3.2.6
The Upper Address (IIM_UA) register contains the top part of the address of the e-Fuse bit to be
programmed or the word to be sensed in an explicit sense cycle. Programming is done on a bit-basis, so
Freescale Semiconductor
PRG_LENGTH
Address: Base + 0x010
Reset
Reset
ESNS_N
ESNS_0
ESNS_1
Field
PRG
[2:0]
W
W
R
R
16
0
0
0
0
0
Upper Address (IIM_UA) Register
Program Length. These thee bits define the length of the program pulse.
PRG_LENGTH × (period of 32 kHz clock).
Explicit Sense—Normal. Writing 1 to this bit initiates an unstressed (normal) explicit sense cycle. Reading this
bit always returns 0. FSM generates a done signal when the operation completes. This bit is cleared
automatically by hardware when sense operation completes. Only one of ESNS_N, ESNS_0, ESNS_1, and
PRG can be asserted. Otherwise, ESNS_E is asserted to indicate this error.
0 Return 0 for all read (read); No meaning (write).
1 Initiate an unstressed explicit sense cycle (write).
Explicit Sense—0 Stressed. Writing 1 to this bit initiates a 0-stressed explicit sense cycle. Reading this bit
always returns 0. FSM generates a done signal when the operation completes. This bit is cleared
automatically by hardware when sense operation completes. During 0-stressed explicit sense cycles, the
EPM_READSENSE0 signal is asserted to the fuse banks. Only one of ESNS_N, ESNS_0, ESNS_1, and
PRG can be asserted. Otherwise, ESNS_E is asserted to indicate this error.
0 Return 0 for all read (read); No meaning (write).
1 Initiate a 0-stressed explicit sense cycle (write).
Explicit Sense—1 Stressed. Writing 1 to this bit initiates a 1-stressed explicit sense cycle. Reading this bit
always returns 0. FSM generates a done signal when the operation completes. This bit is cleared
automatically by hardware when sense operation completes. During 1-stressed explicit sense cycles, the
EPM_READSENSE1 signal is asserted to the fuse banks. Only one of ESNS_N, ESNS_0, ESNS_1, and
PRG can be asserted. Otherwise, ESNS_E is asserted to indicate this error.
0 Return 0 for all read (read); No meaning (write).
1 Initiate a 1-stressed explicit sense cycle (write).
Program. Writing 1 to this bit initiates a fuse program cycle. Reading this bit always returns 0. FSM generate
a done signal when the operation complete. This bit is cleared automatically by hardware when program
operation completes. Only one of ESNS_N, ESNS_0, ESNS_1, and PRG can be asserted. Otherwise,
ESNS_E is asserted to indicate this error.
0 Return 0 for all read (read); No meaning (write).
1 Initiate a program cycle (write).
17
0
0
0
0
1
18
0
0
0
0
2
19
0
0
0
0
3
Figure 17-5. Fuse Control (IIM_FCTL) Register
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 17-6. IIM_FCTL field descriptions
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
24
8
0
0
0
0
PRG_LENGTH[2:0]
25
9
0
0
0
10
26
0
0
1
11
27
0
0
1
Access: Supervisor read/write
ESNS
_N
12
28
0
0
0
ESNS
_0
13
29
0
0
0
ESNS
_1
14
30
IIM/Fusebox
0
0
0
PRG
15
31
17-7
0
0
0