MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 724

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Serial Controller (PSC)
way as they do in an SPI, and their values must be the same as the CPOL and CPHA bits in the SPI device
communicating with the PSC. The SICR[UseEOF] bit has an effect only when SICR[MSTR] equals 1 for
master mode. If the UseEOF bit is cleared, only one data word (8, 12, 16, or 32 bit width depending on the
SICR[SIM] field) sent before slave select (SS) goes high/inactive.
When SICR[UseEOF] equals 1, the number of bytes transferred prior to SS going high is controlled by the
EOF flag inside the Tx FIFO.
As the PSC reads bytes out of the Tx FIFO, it holds SS low/active until it transmits a byte whose EOF flag
is set. In this mode, there is virtually no limit on how many bytes can be sent in one SPI transfer. EOF mode
is supported to enable the user to transfer an increased quantity of data in one frame. When using EOF
mode, the PSC reads bytes out of the Tx FIFO, the SS signal is driven low (asserted), and the SPI continues
to transmit. The last data of the frame is sent after the EOF flag is set. This presence of the EOF flag shows
that the last data in the frame has been reached. EOF mode should not be used for single data transfers,
and is limited by data packages that must be bigger than the chosen codec size. When using EOF mode,
the next data EOF frame flag should not be used to toggle the SS signal after every individual transfer when
in EOF mode. If the SPI is used to transmit data in single codec size packages, the UseEOF bit in the SICR
register should be cleared (0), and the value of the SIM field in this register should be set for the
appropriate data transfer size.
To mark a data word with the EOF flag during a IPB transfer, set the IRCR2[NXTEOF] bit before writing
the last data word to the TX FIFO. This bit is cleared after the next write access to the TX FIFO.
The SICR[SHDIR] bit controls the shift direction in SPI mode, as it does in the non-SPI codec modes. The
DTS1, ESAI, ClkPol, SyncPol, CellSlave, and Cell2xClk bits in the SICR register have no effect in SPI
mode.
In SPI master mode, the BCLK (SCK) frequency is generated by dividing down the MCLK frequency; see
Section 25.5.2.2, “Codec Clock and FrameSync Generation.”
DSCLK delay and the DTL delay must be defined. The DSCLK defines the delay between the SS going
active and the first BCLK (SCK) clock pulse transition. The DSCLK delay is created by dividing down
the MCLK frequency. The delay between consecutive transfers is created by dividing down the IPB clock
frequency. For more information about the delay generation, see the description of the CTUR,
CCR
In SPI master mode the PSC controls the serial data transfers. If the Tx FIFO becomes empty (underrun)
or the Rx FIFO becomes full (overflow) in the middle of a multi-byte transfer, rather than set the Tx
underrun or Rx overflow status bits, the PSC keeps the slave select signal low/active and stops the SCK
25-46
registers.
MPC5125 Microcontroller Reference Manual, Rev. 2
DTL =
where:
CT[0:15] = {CTUR[0:7], CTLR[0:7]}
IPB clock frequency
CT[0:15] + 2
DSCKL delay =
CCR[0:7] + 1
+
MCLK
MCLK frequency
In addition to the BCLK generation, the
3
Freescale Semiconductor
CTLR
Eqn. 25-6
and