MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 922

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
If software removes the queue head with the H-bit set, it must select another queue head linked into the
schedule and set its H-bit. This should be completed before removing the queue head. The requirement is
that software keep one queue head in the asynchronous schedule, with its H-bit set. At the point software
has removed one or more queue heads from the asynchronous schedule, it is unknown whether the host
controller has a cached pointer to them. Similarly, it is unknown how long the host controller might retain
the cached information, as it is implementation dependent and may be affected by the actual dynamics of
the schedule load. Therefore, once software has removed a queue head from the asynchronous list, it must
retain the coherency of the queue head (link pointers). It cannot disturb the removed queue heads until it
knows that the host controller does not have a local copy of a pointer to any of the removed data structures.
The method software uses to determine when it is safe to modify a removed queue head is to handshake
with the host controller. The handshake mechanism allows software to remove items from the
asynchronous schedule, then execute a simple, lightweight handshake used by software as a key that it can
free (or reuse) the memory associated the data structures it has removed from the asynchronous schedule.
The handshake is implemented with three bits in the host controller. The first bit is a command bit
(interrupt on async advance doorbell bit in the USB_USBCMD register) that allows software to inform the
host controller that something has been removed from its asynchronous schedule. The second bit is a status
bit (interrupt on async advance bit in the USB_USBSTS register) that the host controller sets after it has
released all on-chip state that may potentially reference one of the data structures recently removed. When
the host controller sets this status bit, it also clears the command bit. The third bit is an interrupt enable
(interrupt on async advance bit in the USB_USBINTR register) that is matched with the status bit. If the
status bit is set and the interrupt enable bit is set, the host controller asserts a hardware interrupt.
Figure 32-57
the schedule using the algorithm above. Before the unlink operation, the host controller has a copy of
queue head A.
The unlink algorithm requires that as software unlinks each queue head, the unlinked queue head is loaded
with the address of a queue head that remains in the asynchronous schedule.
When the host controller observes that doorbell bit being set, it makes a note of the local reachable
schedule information. In this example, the local reachable schedule information includes both queue heads
(A & B). It is sufficient the host controller can set the status bit (and clear the doorbell bit) as soon as it has
traversed beyond current reachable schedule information (traversed beyond queue head (B) in this
example).
32-94
End UnlinkQueueHead
-- software is unlinking a consecutive series of
-- queue heads, QHeadNext must be set by software to
-- the queue head remaining in the schedule.
--
-- This algorithm unlinks a queue head from a circular list
--
pQueueHeadPrevious.HorizontalPointer = pQueueHeadToUnlink.HorizontalPointer
pQueueHeadToUnlink.HorizontalPointer = pQHeadNext
illustrates a general example where consecutive queue heads (B and C) are unlinked from
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor