MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 241

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.2.1.13
The DMA Interrupt Request High (DMAINTH) and DMA Interrupt Request Low (DMAINTL) registers
provide a bit map for the implemented 64 channels signaling the presence of an interrupt request for each
channel. DMAINTH supports channels 63–32, while DMAINTL covers channels 31–00. The
DMA_ENGINE signals the occurrence of a programmed interrupt upon the completion of a data transfer
as defined in the transfer control descriptor by setting the appropriate bit in this register. The outputs of
this register are directly routed to the platform’s interrupt controller. During the execution of the interrupt
service routine associated with any given channel, it is the software’s responsibility to clear the appropriate
bit, negating the interrupt request. Typically, a write to the DMACINT register in the interrupt service
routine is used for this purpose.
The state of any given channel’s interrupt request is directly affected by writes to this register; it is also
affected by writes to the DMACINT register. On writes to the DMAINT, a 1 in any bit position clears the
corresponding channel’s interrupt request. A 0 in any bit position has no effect on the corresponding
channel’s current interrupt status. The DMACINT register is provided so the interrupt request for a single
channel can easily be cleared without the need to perform a read-modify-write sequence to the DMAINTH
or DMAINTL registers.
See
Freescale Semiconductor
Address: Base + 0x001F
CDNE[6:0]
Figure 9-15
Reset
Field
W
R
DMA Interrupt Request (DMAINTH, DMAINTL)
Clear DONE Status Bit
0–63
64–127 Clears all the TCD.DONE bits.
0
0
0
and
Figure
Clears the corresponding channel’s DONE bit.
Figure 9-14. DMA Clear DONE Status Register (DMACDNE)
1
0
0
9-16, and
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 9-15. DMACDNE field descriptions
Table 9-16
0
0
2
for the DMAINT definition.
0
0
3
Description
CDNE[6:0]
0
0
4
0
0
5
Direct Memory Access (DMA)
Access: User read/write
0
0
6
0
0
7
9-21