MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 400

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
DMA. If the frame is a runt (due to collision) or is rejected by address recognition, the receive FIFO is
notified to reject the frame. Thus, no collision fragments are presented except late collisions, which
indicate serious LAN problems.
During reception, the Ethernet controller checks for various error conditions and after the entire frame is
written into the FIFO, a 32-bit frame status word is written into the FIFO. This status word contains the
M, BC, MC, LG, NO, SH, CR, OV and TR status bits and the frame length.
Receive buffer (RXB, FEC only) and frame (RFINT, FEC only) interrupts may be generated if enabled by
the ETH_IMASK register. BABR and RFIFO_ERROR are receive error interrupts. Receive frames are not
truncated if they exceed the MAX_FL byte length; however, the BABR interrupt occurs and the LG bit in
the receive BD is set.
When the receive frame is complete, the FEC sets the l bit in the receive BD, writes the other frame status
bits into the receive BD, and clears the E bit. Next, the Ethernet controller generates a maskable interrupt
(RFINT bit in ETH_IEVENT, maskable by RFIEN bit in ETH_IMASK), indicating a frame has been
received and is in memory. The Ethernet controller then waits for a new frame.
The Ethernet controller receives serial data LSB first.
14.6.3
Ethernet Address Recognition
The FEC filters the received frames based on destination address (DA) type — individual (unicast), group
(multicast), or broadcast (all-ones group address). The difference between an individual address and a
group address is determined by the I/G bit in the destination address field. A flowchart for address
recognition on received frames is illustrated in the following figures.
Address recognition is accomplished through the use of the receive block and microcode running on the
descriptor controller. The flowchart shown in
Figure 14-30
illustrates the address recognition decisions
made by the receive block, while
Figure 14-31
illustrates the decisions made by the descriptor controller.
If the DA is a broadcast address and broadcast reject (BC_REJ bit is deasserted, the frame is accepted
unconditionally, as shown in
Figure
14-30. Otherwise, if the DA is not a broadcast address, the descriptor
controller runs the address recognition subroutine, as shown in
Figure
14-31.
If the DA is a group (multicast) address and flow control is disabled, the descriptor controller performs a
group hash table lookup using the 64-entry hash table programmed in ETH_GADDR1 and
ETH_GADDR2. If a hash match occurs, address recognition hash match bar (AR_HM_B) is set to 0 and
the receiver accepts the frame. If flow control is enabled, the descriptor controller does an exact address
match check between the DA and the designated pause DA in registers FDXFC_DA1 and FDXFC_DA2.
If a pause DA exact match occurs, the address recognition exact match bar (AR_EM_B) is set to 0. If the
receive block determines the received frame is a valid pause frame, the frame is rejected. The receiver
detects a pause frame with the DA field set to the designated pause DA or the unicast physical address.
If the DA is the individual (unicast) address, the descriptor controller performs an individual exact match
comparison between the DA and 48-bit physical address that you program in the ETH_PADDR1 and
ETH_PADDR2 registers. If an exact match occurs, AR_EM_B is set to 0; otherwise, the descriptor
controller does an individual hash table lookup using the 64-entry hash table programmed in the
MPC5125 Microcontroller Reference Manual, Rev. 2
14-44
Freescale Semiconductor