MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 513

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The interrupt control register is common to three MPC5125 I
internal interrupt that can be routed to the CPU if the respective IE bit is set to 1.
Reset condition is IE set, and all other enable bits clear.
The BNBE bit lets the module generate an interrupt when the bus becomes not-busy. This implies receipt
of a STOP condition, for which the module normally does not generate an interrupt. Because bus-not-busy
is an idle condition, it is necessary for software responding to this interrupt to clear the BNBE bit to clear
the interrupt condition. Otherwise, the interrupt condition persists until another I
19.3.1.7
Freescale Semiconductor
Address: Base + 0x64
Reset
Reset
BNBE3
BNBE2
BNBE1
Field
IE3
IE2
IE1
W
W
R
R
16
0
0
0
0
0
I
2
Bus Not Busy Enable 3. This bit lets module 3 generate an interrupt when the bus is not busy. BNBE3
indicates an idle condition.
To clear the interrupt, software must write 0 to the bit position.
Reset disables BNBE3.
Interrupt Enable 3, This bit routes the interrupt for module 3 to the CPU.
Clear by writing 0 to this bit.
Reset enables IE3.
Bus Not Busy Enable 2, This bit lets module 2 generate an interrupt when the bus is not busy. BNBE2
indicates an idle condition.
To clear the interrupt, software must write 0 to the bit position.
Reset disables BNBE2.
Interrupt Enable 2, This bit routes the interrupt for module 2 to the CPU.
Clear by writing 0 to this bit.
Reset enables IE2.
Bus Not Busy Enable 1, This bit lets module 1 generate an interrupt when the bus is not busy. BNBE1
indicates an idle condition.
To clear the interrupt, software must write 0 to the bit position.
Reset disables this bit.
Interrupt Enable 1, This bit routes the interrupt for module 1 to the CPU.
Clear by writing 0 to this bit.
Reset enables IE1.
C Filter Register (I2C_MIFR)
17
0
0
0
0
1
18
0
0
0
0
2
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 19-15. I
Table 19-10. I2C_ICR field descriptions
FR3
20
4
0
0
0
FR2
21
0
0
0
5
2
FR1
C Filter Register (I2C_MIFR)
22
0
0
0
6
FR0
23
0
0
0
7
Description
24
8
0
0
0
0
2
C modules. Each module generates an
25
9
0
0
0
0
10
26
0
0
0
0
11
27
0
0
0
0
2
C transaction is initiated.
12
28
Inter-Integrated Circuit (I
0
0
0
0
Access: User read/write
13
29
0
0
0
0
14
30
0
0
0
0
19-21
15
31
0
0
0
0
2
C)