MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 36

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System Configuration and Memory Map (XLBMEN + Mem Map)
Changing the value of IMMRBAR changes the location of the Local Access Windows Target Interface.
The address of the IMMRBAR Register is the contents of the IMMRBAR register, itself. A Special
Purpose Register, SPR311, is specifically provided such that a copy of IMMRBAR can be maintained in
a register that does not move in the memory map.
2.2.2
The local access windows perform target mapping for transactions within the local address space. No
address translation is performed by the local access windows.
2.2.3
The internal memory map base address register (IMMRBAR) defines a window that is used to access all
memory-mapped configuration, control, and status registers, referred as internal memory map registers or
IMMR. The window is always enabled with a fixed size of 1
with Window 0. This window always takes precedence over all local access windows. The IMMRBAR
2-2
Window
Number
10
11
12
0
1
2
3
4
5
6
7
8
9
Address Translation and Mapping
Window into Configuration Space
It is generally a programming error to overlap the addressing range of the
Local Access Windows. There is nothing to prevent software from
programming overlapping addresses.
It is the responsibility of the system software to properly maintain e300
special purpose register 311 (SPR311 -MBAR) such that its contents are the
same as the contents of the IMMRBAR Register.
Offset to
0x02C
0x03C
0x0C4
0x0C8
0x0A0
0x0A4
IMMR
0x000
0x020
0x024
0x028
0x030
0x034
0x038
0x040
LocalPlus Bus CS0 Access Window Register
LocalPlus Bus CS1 Access Window Register
LocalPlus Bus CS2 Access Window Register
LocalPlus Bus CS3 Access Window Register
LocalPlus Bus CS4 Access Window Register
LocalPlus Bus CS5 Access Window Register
LocalPlus Bus CS6 Access Window Register
LocalPlus Bus CS7 Access Window Register
DDR SDRAM Local Access Window Base Address Register
DDR SDRAM Local Access Window Attributes Register
SRAM Base Address Register
NFC Base Address Register
Configuration registers (IMMRBAR)
LocalPlus Bus Boot Access Window Register
Table 2-1. Local Access Windows Target Interface
MPC5125 Microcontroller Reference Manual, Rev. 2
Target Interface
NOTE
NOTE
MB.
There is no attributes register associated
Fixed 256 KB window size
Fixed 1 MB window size
Fixed 1 MB window size
Freescale Semiconductor
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