MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 237

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.2.1.6
The DMA Clear Enable Request (DMACERQ) register provides a simple memory-mapped mechanism to
clear a given bit in the DMAERQH and DMAERQL registers to disable the DMA request for a given
channel. The data value on a register write causes the corresponding bit in the DMAERQH or DMAERQL
register to be cleared. A data value of 64 to 127 (regardless of the number of implemented channels)
provides a global clear function, forcing the entire contents of the DMAERQH and DMAERQL registers
to be cleared, disabling all DMA request inputs. Reads of this register return all 0s. See
Table 9-9
9.2.1.7
The DMASEEI register provides a simple memory-mapped mechanism to set a given bit in the DMAEEIH
and DMAEEIL registers to enable the error interrupt for a given channel. The data value on a register write
causes the corresponding bit in the DMAEEIH or DMAEEIL register to be set. A data value of 64 to 127
(regardless of the number of implemented channels) provides a global set function, forcing the entire
Freescale Semiconductor
Address: Base + 0x0018
Address: Base + 0x0019
CERQ[6:0]
SERQ[6:0]
Reset
Reset
Field
Field
W
W
R
R
for the DMACERQ definition.
DMA Clear Enable Request (DMACERQ)
DMA Set Enable Error Interrupt (DMASEEI)
Set Enable Request
0–63
64–127 Sets all the bits in the DMAERQH and DMAERQL registers.
Clear Enable Request
0–63
64–127 Clears all the bits in the DMAERQH and DMAERQL registers.
0
0
0
0
0
0
Sets the corresponding bit in the DMAERQH or DMAERQL register.
Clears the corresponding bit in the DMAERQH or DMAERQL register.
Figure 9-8. DMA Clear Enable Request Register (DMACERQ)
Figure 9-7. DMA Set Enable Request Register (DMASERQ)
1
0
0
1
0
0
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 9-8. DMASERQ field descriptions
Table 9-9. DMACERQ field descriptions
0
0
0
0
2
2
0
0
0
0
3
3
Description
Description
CERQ[6:0]
SERQ[6:0]
0
0
0
0
4
4
0
0
0
0
5
5
Direct Memory Access (DMA)
Access: User read/write
Access: User read/write
0
0
0
0
6
6
Figure 9-8
0
0
0
0
7
7
and
9-17