MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 629

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.4.13 Recovery from Deep Sleep Mode
The MSCAN can wake up the Power Architecture from deep sleep mode via the wake-up interrupt. This
interrupt can only occur if the MSCAN is in Sleep Mode (SLPRQ = 1 and SLPAK = 1), the wake-up
option is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1).
When there is recessive to dominant change in CAN_RX pin, there is a wake-up interrupt generated
asynchronously. Power Architecture can then be waken up from deep sleep mode by that interrupt.
After Power Architecture be waken up from deep sleep mode, it can enable the clocks of MSCAN and put
MSCAN into normal operation mode again.
22.4.14 MSCAN Initialization
The procedure to initially start up the MSCAN module out of reset is as follows:
If the configuration of the registers that are writable in initialization mode only needs to be changed when
the MSCAN module is in normal mode, do the following:
22.4.15 Bus-Off Recovery
The bus-off recovery is configurable: the bus-off state can be left automatically or on request.
For reasons of backwards compatibility the MSCAN defaults to automatic recovery after reset. In this
case, the MSCAN becomes error active again after counting 128 occurrences of 11 consecutive recessive
bits on the CAN bus. These two events may occur in any order.
Freescale Semiconductor
1. Assert CANE.
2. Write to the configuration registers in initialization mode.
3. Clear INITRQ to leave initialization mode and enter normal mode.
1. Make sure that the MSCAN transmission queue becomes empty and bring the module into sleep
2. Enter initialization mode: Assert INITRQ and await INITAK.
3. Write to the configuration registers in initialization mode.
4. Clear INITRQ to leave initialization mode and continue in normal mode.
mode by asserting SLPRQ and awaiting SLPAK.
It must be guaranteed that the Power Architecture only clears the bit causing
the current interrupt. RXFIF interrupt clear has the side effect of moving the
receive buffer from the current to the next. Clearing a TXExIF flag also
clears the corresponding ABTAKx. When a TXExIF flag is set, the
corresponding ABTRQx bit is cleared
Only MSCAN modules 1 and 2 can wake up the MPC5125 from deep sleep.
MSCAN modules 3 and 4 cannot wake up the MPC5125 from deep sleep
mode.
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
NOTE
MSCAN
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