MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 651

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

23.8.1
The ECC engine determines if a page is correctable. If correctable, it corrects error bits, and indicates error
number, otherwise, the Corfail bit is asserted as shown in
management strategy to work, it may be necessary for the processor to obtain this information.
The error corrector writes the status word to a byte location to the SRAM buffer, defined by
ECC_SRAM_ADDR + 0x07. It is selectable if the status is written or not with bit ECC_SRAM_REQ.
Both fields are part of config register FLASH_CONFIG. In case the status is written to the SRAM buffer,
it becomes effectively part of the flash data, and will be processed like the flash data. Most likely, the status
byte will be written to memory as part of the page header. Once in memory, the ECC status is visible to
the CPU, while CPU parsing the rest of the flash header too. No interrupt on error or status is available
because this would increase the interrupt load on the CPU. (The interrupt would be independent of the
CMD_DONE_IRQ interrupt.) It is not possbile to stop reading when ECC failed.
The organization of the status byte is given in
23.8.2
23.8.2.1
This command is used to read pages from the NAND flash.
read operation.
Freescale Semiconductor
Bitfield
•
•
•
•
5:0
7
Compatible with 8-wide SLC and MLC devices with page size of 4 KB and larger
Compatible with 16-wide SLC and MLC devices with page size of 2048 bytes + 64 bytes spare
Compatible with 16-wide SLC and MLC devices with page size of 4 KB and larger
Not compatible with devices with 512 bytes page size.
Error Corrector Status
NFC Basic Commands
Page Read
error_count
Corfail
Name
0 Page has been successfully corrected.
1 Page is uncorrectable.
Number of errors that have been corrected in this page.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 23-19. ECC status word
Table
23-19.
Table
Figure 23-18
Meaning
23-19. In order for a bad block
is the general flow chart of the
NAND Flash Controller (NFC)
23-21