MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 378

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
14.3.5.11 Receive Hash (ETH_R_HASH) Register
The read-only Receive Hash (ETH_R_HASH) register provides address recognition information from the
receive block about the frame currently being received. This field is read by the FEC. These bits provide
the FEC with information used in the address recognition subroutine.
14-22
Address: Base + 0x088
MII_MODE
BC_REJ
Reset
Reset
PROM
LOOP
Field
FCE
DRT
W
W
R FCE_
R
DC
16
0
0
Flow control enable. If asserted, the receiver detects pause frames. The transmitter stops transmitting data
frames for a given duration when pause frames are detected.
Broadcast frame reject. If asserted, frames with DA = FFFF_FFFF_FFFF are rejected unless the PROM bit is
set. If BC_REJ and PROM equal 1 individually, frames with broadcast DA are accepted and the MISS (M) bit is
set in the receive buffer descriptor.
Promiscuous mode. All frames are accepted, regardless of address matching.
Selects external interface mode.
0 7-wire mode (used only for serial 10Mbit/s)
1 MII or RMII mode as indicated by the RMII_MODE bit
Disable receive on transmit.
0 Receive path operates independently of transmit (use for full-duplex or to monitor transmit activity in
1 Disable reception of frames while transmitting (normally used for half-duplex mode).
Internal loopback. If set, transmitted frames are looped back internal to the device and the transmit output
signals are not asserted. The system clock is substituted for the TX_CLK when loop is asserted. DRT must be
set to 0 when asserting loop.
MULT-
CAST
half-duplex mode).
17
0
1
18
0
2
Table 14-15. ETH_R_CNTRL field descriptions (continued)
Figure 14-12. Receive Hash (ETH_R_HASH) Register
19
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
HASH
21
0
5
22
0
6
23
0
7
Description
24
8
0
0
25
9
0
0
10
26
0
0
11
27
0
0
12
28
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
14
30
0
0
15
31
0
0