MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 931

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

This traversal state machine applies to all queue heads, regardless of transfer type or whether split
transactions are required. The following sections describe each state. Each state description describes the
entry criteria. The Execute Transaction state (see
basic requirements for all endpoints.
and
Execute Transaction state for endpoints requiring split transactions.
32.6.9.1
A queue head can be referenced from the physical address stored in the USB_ASYNCLISTADDR register
(see
Additionally, it may be referenced from the Next Link Pointer field of an iTD, siTD, FSTN or another
Queue Head. If the referencing link pointer has the Typ field set to indicate a queue head, it is assumed to
reference a queue head structure as defined in
While in this state, the host controller performs operations to implement empty schedule detection (see
Section 32.6.7.3, “Empty Asynchronous Schedule
“Operational Model for NAK
conducts the following queries for empty schedule detection:
When these criteria are met, the host controller stops traversing the asynchronous list (as described in
Section 32.6.7.3, “Empty Asynchronous Schedule
controller continues schedule traversal. If the queue head is not an interrupt and the H-bit is a one and the
Reclamation bit is a one, then the host controller sets the Reclamation bit in the USB_USBSTS register to
a zero before completing this state. The operations for reloading of the Nak Counter are described in detail
in
This state is complete when the queue head has been read on-chip.
32.6.9.2
To advance the queue, the host controller must find the next qTD, adjust pointers, perform the overlay and
write back the results to the queue head.
Freescale Semiconductor
Section 32.6.8, “Operational Model for NAK Counter.”
•
•
•
•
•
Section 32.6.11.2, “Split Transaction Interrupt,”
Section 32.2.4.8, “Current Asynchronous List Address Register
Valid static endpoint state
For the first use of a queue head, software may zero out the queue head transfer overlay, then set
the Next qTD Pointer field value to reference a valid qTD.
If queue head is not an interrupt queue head (i.e., S-mask is a zero), and
The H-bit is a one, and
The Reclamation bit in the USB_USBSTS register is 0.
Fetch Queue Head
Advance Queue
Prior to software placing a queue head into either the periodic or
asynchronous list, software must ensure the queue head is properly
initialized. Minimally, the queue head should be initialized to the following
(see
Section 32.5.6, “Queue Head,”
MPC5125 Microcontroller Reference Manual, Rev. 2
Counter”). After the queue head has been fetched, the host controller
Section 32.6.11.1, “Split Transactions for Asynchronous Transfers,”
Figure
NOTE
Section 32.6.9.3, “Execute
Detection”) and Nak Counter reloads
Detection”). When the criteria are not met, the host
for layout of a queue head):
describe details of the required extensions to the
32-49.
Universal Serial Bus Interface with On-The-Go
(USB_ASYNCLISTADDR)”).
Transaction”) describes the
(Section 32.6.8,
32-103