MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 264

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
Display Interface Unit (DIU)
10.2
Table 10-1
timing information for assertion and negation.
10.3
10.3.1
Table 10-2
10-2
DIU_CLK
DIU_VSYNC
DIU_HSYNC
DIU_DE
DIU_LD[23:0]
Refer to the system clock chapter for details on this clock.
Signal
1
External Signal Description
Memory Map and Register Definition
describes the DIU input and output signals, the meaning of their different states, and relative
shows the register memory map for the DIU memory controller.
Memory Map
I/O
O
O
O
O
O
Pixel clock. This signals is used to drive the display panel.
Vertical synchronizing signal. This signal indicates the beginning of a new frame. This signal may
alternately be programmed to output a composite sync (CSYNC) signal by programming
SYN_POL[BP_VS]. See
(SYN_POL),”
synchronizing signals to form a composite synchronizing signal. It includes both the HSYNC pulse
and the VSYNC pulse. The default output is DIU_VSYNC.
State
Meaning
Timing
Horizontal synchronizing signal. This signal indicates the beginning of a new line. This signal may
alternately be programmed to output a composite sync (CSYNC) signal by programming
SYN_POL[BP_HS]. See
(SYN_POL),”
synchronizing signals to form a composite synchronizing signal. It includes both the HSYNC pulse
and the VSYNC pulse. The default output is DIU_HSYNC.
State
Meaning
Timing
Data enable. This signal qualifies the data on the data output signals (DIU_LD)
State
Meaning
Data output signals.
• DIU_LD[23:16] = Red[7:0].
• DIU_LD[15:8] = Green[7:0].
• DIU_LD[7:0] = Blue[7:0].
Table 10-1. Display Interface Detailed Signal Descriptions
DIU_LD[23] is the most significant bit, and DIU_LD[16] is the least significant bit of the Red
component.
DIU_LD[15] is the most significant bit, and DIU_LD[8] is the least significant bit of the Green
component.
DIU_LD[7] is the most significant bit, and DIU_LD[0] is the least significant bit of the Blue
component.
MPC5125 Microcontroller Reference Manual, Rev. 2
Asserted at the beginning of a new frame.
Asserted with the first cycle of the frame period. The length of the pulse is programmable.
Asserted at the beginning of a new line.
Asserted with the first cycle of a new line. The length of the pulse is programmable.
Deasserted: DIU_LD data is not valid.
Asserted: DIU_LD data is valid.
for more information. The composite sync signal combines the horizontal and vertical
for more information. The composite sync signal combines the horizontal and vertical
Section 10.3.3.16, “Synchronization Signals Polarity Register
Section 10.3.3.16, “Synchronization Signals Polarity Register
Description
Freescale Semiconductor