MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 207

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.2.1.5
The Arbiter Interrupt Definition Register (AIDR) determines the interrupt that responds to different error
conditions. Setting a bit defines the corresponding interrupt as an MCP interrupt ; clearing a bit defines
the corresponding interrupt as a regular interrupt.
Freescale Semiconductor
Address: Base + 0x10
Reset
Reset
ETEA
Field
ECW
RES
DTO
ATO
AO
W
W
R
R
16
0
0
0
0
0
Arbiter Interrupt Definition Register (AIDR)
Transfer error. External TEA. Reports on detection of transfer error assertion of TEA signal by one of the
slaves.
0 No transfer error detected TEA signal is not asserted by one of the slaves.
1 Transfer error detected TEA signal is asserted by one of the slaves.
Reserved transfer type. Reports on transaction with reserved transfer type. See
Transaction Type,”
0 No transaction with reserved transfer type occurred.
1 Transaction with reserved transfer type occurred.
External control word transfer type. Reports on transaction with external control word transfer type. See
Section 8.3.2.6, “Illegal (ECIWX/ECOWX) Transaction Type,”
0 No transaction with external control word transfer type occurred.
1 Transaction with external control word transfer type occurred.
Address Only transfer type. Reports on transaction with address only transfer type. See
“Address-Only Transaction Type,”
0 No transaction with address only transfer type occurred.
1 Transaction with address only transfer type occurred.
Data time out. Reports on data tenure time out.
0 Data time out timer is not expired.
1 Data time out timer is expired.
Address time out. Reports on address tenure time out.
0 Address time out timer is not expired.
1 Address time out timer is expired.
17
0
0
0
0
1
18
0
0
0
0
2
Figure 8-5. Arbiter Interrupt Definition Register (AIDR)
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
for more information.
20
4
0
0
0
0
Table 8-5. AER field descriptions
21
0
0
0
0
5
for more information.
22
0
0
0
0
6
Figure 8-5
23
0
0
0
0
7
Description
24
8
0
0
0
0
shows the fields of AIDR.
25
9
0
0
0
0
for more information.
ETEA RES ECW
10
26
0
0
0
11
27
0
0
0
Section 8.3.2.5, “Reserved
CSB Arbiter and Bus Monitor
12
28
0
0
0
Access: User read/write
Section 8.3.2.4,
AO
13
29
0
0
0
DTO
14
30
0
0
0
ATO
15
31
0
0
0
8-7