MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 304

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Display Interface Unit (DIU)
A display parameter error interrupt is generated if the user sets the display parameters incorrectly.
Table 10-43
interrupt is detected, the user can turn off the DIU (program the DIU_MODE to 0), correct the wrong
parameter(s), and turn it on again. The DIU is initialized internally.
10.4.12 Dynamic Priority Generation
The multi-port DRAM controller has built-in arbiters that use a 4-bit priority signal (i.e., 16 levels of
priority). The DRAM controller tries to service the request with the highest priority first. The task of
setting the priorities is done by the DRAM Controller Priority Manager block, the priority manager. It
dynamically sets the priorities of the DRAM buses in such a way that bandwidth is divided fairly and each
master receives its fair share of the bandwidth. Programming the look-up tables in the priority manager
allows controlling relative priority to other channels and the average share of the bandwidth the current
master gets.
The DIU outputs a 4-bit priority signal to the priority manager. The priority is a function of the internal
input buffer filling level (buffer full → low priority, buffer empty → high priority). The buffer filling level
ranges from 0 to 7 and its used to select a LUT component from the PLUT register as the priority. Filling
level 0 selects PRIORITY_0 and filling level 7 selects PRIORITY_7.
The priority manager can be programmed to take the DIU priority output directly (option 1) or to follow
the normal priority schema (option 2). It is recommended to use option 2, the default option.
To use option 1, the user should set PRIOMAN_CONFIG2[DIU-OVERRULE] (refer to DRAM
Controller Priority Manager chapter), and program a set of priority values in the PLUT register
10-42
•
•
•
•
UNDRUN—Under Run Exception
PARERR—Display Parameter Error
LS_BF_VS—Lines Before VSYNC
WB_PEND—Writeback Pending
lists the parameter error conditions under different DIU operating modes. When a PARERR
Mode 1 & 2
Mode 2 & 3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 10-43. Parameter Error Conditions
DELTA_XI > DELTA_XS
DELTA_YI > DELTA_YS
DELTA_XI + OFFSET_XD > DELTA_X
DELTA_YI + OFFSET_YD > DELTA_Y
DELTA_XI + OFFSET_XI > DELTA_XS
DELTA_YI + OFFSET_YI > DELTA_YS
DELTA_XI > DELTA_X_WB
DELTA_YI > DELTA_Y_WB
DELTA_XI + OFFSET_XD > DELTA_X_WB
DELTA_YI + OFFSET_YD > DELTA_Y_WB
DELTA_XI + OFFSET_XI > DELTA_XS
DELTA_YI + OFFSET_YI > DELTA_YS
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