MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 555

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.2.1.2.2
21.2.1.2.3
Freescale Semiconductor
Address: Base + 0x104
Address: Base + 0x108
ADDRESS
Reset
Reset
Reset
Reset
FLUSH
START
Field
Field
CSX
R/W
W
W
W
W
R
R
R
R
16
16
0
0
0
0
0
0
0
0
SCLPC Start Address (LPC_SCLPC_SA) Register
SCLPC Control (LPC_SCLPC_C) Register
The address of the first byte in the packet to be sent.
Note: START ADDRESS needs to be either a multiple of BPT setting (see
This field should be written with the chip select number associated with each SCLPC transaction.
Note: LPC configuration registers associated with this CS also affect SCLPC transactions. The two work
If set to 1, this bit enables the assertion of the DMA request at the completion of a read packet, regardless of
the actual state of the physical FIFO alarm. The DMA request deasserts after the FIFO empties.
Read/Write bar that controls the direction of the SCLPC transaction.
0 SCLPC writes to the device; i.e., FIFO transmit.
1 SCLPC reads from the device; i.e., FIFO receive. (Default)
17
17
0
0
0
0
0
0
1
1
together.
Figure 21-12. SCLPC Start Address (LPC_SCLPC_SA) Register
18
18
0
0
0
0
0
0
2
2
Figure 21-13. SCLPC Control (LPC_SCLPC_C) Register
19
19
0
0
0
0
0
0
3
Table 21-13. LPC_SCLPC_SA field descriptions
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 21-14. LPC_SCLPC_C field descriptions
20
20
4
0
0
4
0
0
0
0
21
21
0
0
0
0
0
5
5
CSX
22
22
0
0
0
0
0
6
6
START ADDRESS
START ADDRESS
DAI
23
23
0
0
0
0
7
7
Description
Description
24
24
8
0
0
8
0
0
0
0
25
25
9
0
0
9
0
0
0
0
10
26
10
26
0
0
0
0
0
11
27
Table
11
27
0
0
0
0
0
LocalPlus Bus Controller (LPC)
21-15) or of 8.
12
28
12
28
0
0
0
0
0
Access: User read/write
Access: User read/write
BPT
13
29
13
29
0
0
0
0
0
FLUSH R/W
14
30
14
30
0
0
0
0
21-15
15
31
15
31
0
0
1
0