MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 656

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NAND Flash Controller (NFC)
1
2
23.8.2.4
This command is used to read the flash ID.
23-26
Optional Register Config:
1.Read status: Set FLASH_CMD_BYTE3(0x3F00)
to 0x70, set FLASH_CMD_CODE(0x3F04) to
1
2.Set STOP_ON_WERR to 1, stop operation on
error.
3.reference
Register
Config
ROW_ADDR3(bolded) is not necessary for some flashes, see datasheets for detail.
If STOP_ON_WERR = 1 and STATUS_BYTE1[0] = 1, the operation stops.
Set FLASH_CMD_BYTE1(0x3F04) to 0x60
Set FLASH_CMD_BYTE2(0x3F00) to 0xD0
Set FLASH_CMD_CODE(0x3F04) to
1
Config ROW_ADDR (0x3F0C),
IRQ_STATUS(ox3F38)(IRQ enable)
0b0100_1110_1101_1000
0b0100_1110_1100_0000
Set BUSY/START(0x3F04) to 1
Figure 23-18
Read ID
Start
for command repeat
Figure 23-22. Flow Chart of Block Erase Operation
MPC5125 Microcontroller Reference Manual, Rev. 2
optional
optional
NFC Actions
optional
2
read STATUS_BYTE1(0x3F1C)
Issue FLASH_CMD_BYTE1 to flash
Issue FLASH_CMD_BYTE2 to flash
Issue FLASH_CMD_BYTE3 to flash
Issue ROW_ADDR to flash
wait for R/B handshake
CMD_DONE_IRQ,
REPEAT_COUNT
=0?
End
Y
N
Freescale Semiconductor
REPEAT_COUNT = REP
EAT_COUNT -1;
ROW_ADDR=ROW_ADD
R+ROW_ADDR_INC,if
ADDR_AUTO_INCR = 1