MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 143

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

occurred, the value corresponding to that interrupt source appears in the BDLC_DLCBSVR register. This
continues until all BDLC interrupt sources have been managed and all bits in the BDLC_DLCBSVR
register are cleared.
Freescale Semiconductor
Address: Base + 0x01
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Reset
Symbol invalid or out of range
CRC error
Cyclical Redundancy Check Byte is used by the receiver(s) of each message to determine if any
errors have occurred during the transmission of the message. If the message is not error free, the
CRC error status is shown in the BDLC_DLCBSVR register.
Loss of arbitration
Loss of arbitration status is entered when a loss of arbitration occurs while the BDLC is
transmitting onto the bus.
Tx data register empty
The Tx data register empty (TDRE) state is used to tell when data has been unloaded from the
BDLC Data Register.
Rx data register full
The Rx data register full (RDRF) state describes when data has been loaded in the BDLC Data
Register.
Received in-frame response (IFR) byte
The BDLC can transmit and receive all four types of in-frame responses. As each byte of an IFR
is received, the BDLC_DLCBSVR register indicates this by setting this state.
Received EOF
When a 280 µs passive period on the bus is received, it signifies an end-of-frame (EOF). When this
occurs, the EOF flag is set.
No interrupts pending
This interrupt cannot generate an interrupt of the CPU.
W
R
0
0
0
Figure 6-3. BDLC State Vector Register (BDLC_DLCBSVR)
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0
0
MPC5125 Microcontroller Reference Manual, Rev. 2
I3
0
2
I2
0
3
I1
0
4
I0
0
5
Byte Data Link Controller (BDLC)
Access: User read-only
0
0
6
0
0
7
6-7