MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 780

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Secure Digital Host Controller (SDHC)
28-8
ERROR_CODE
WRITE_CRC_
CARD_BUS_
RESP_CRC_
READ_CRC_
BUF_READ_
READ_OP_
WR_CRC_
BUF_WR_
CLK_RUN
DONE
Field
RDY
RDY
ERR
ERR
ERR
Read Operation Done. This bit is set at the end of a read operation. When this bit is set, pre-defined data bytes
have been read from the card or a READ TIMEOUT has occurred. Software needs to send a STOP command
to the card if the read command is a MMC or SD card read multi-block command. This bit can be cleared by
writing 1 to it. When this bit is set, the SDHC generates an interrupt request if the READ_OP_DONE interrupt
is enabled in the SDHC_INT_CNTR register. Software must clear this bit to clear the interrupt request.
0 Read operation is in progress or incomplete.
1 Read operation is complete.
Note: When this bit is set, software also needs to check if the read operation completed without error. Also,
Write CRC Error Code. This indicates CRC results from the card at the end of write operations. After receiving
a block of data, the card checks the CRC bit and sends the CRC status. These two bits reflect the CRC status
of the recent written data. If the card returns a negative CRC status, data is not written to the card.
These two bits can be cleared by writing a value of 0b11 to them.
00
01
10
11
Note: The bits are valid only when the SDHC_STATUS[WRITE_CRC_ERR] bit is set.
Card Bus Clock Run. This indicates whether the MMC_SD_CLK clock to the card is running. The clock rate
setting and system configuration can be modified when the clock is turned off by setting the STOP_CLK bit in
SDHC_STR_STP_CLK register. This bit can be cleared only after writing 1 to
SDHC_STR_STP_CLK[STOP_CLK] to stop MMC_SD_CLK.
0 MMC/SD clock is stopped.
1 MMC/SD clock is running.
Polling needs to be done on this bit to assure the SDHC clock is running or stopped.
Buffer Read Ready. This status is set if a buffer (either X buffer or Y buffer) is full during read operations. An
interrupt is triggered for non-DMA transfers if the SDHC_INT_CNTR[BUF_READ_EN] bit is set, or a DMA
request is asserted for DMA transfers.
0 Not ready to read buffer.
1 Ready to read buffer.
Buffer Write Ready. This status is set if a buffer (either X buffer or Y buffer) is available during write operations.
An interrupt is triggered for non-DMA transfers if the SDHC_INT_CNTR[BUF_WRITE_EN] bit is set or a DMA
request is asserted for DMA transfers. This bit is only set when the SDHC is performing write operation to the
card.
0 Not ready to write buffer.
1 Ready to write buffer.
Response CRC Error. This indicates a transmission error occurred on the SD_CMD line during a response
transfer. Writing 1 to this bit clears this bit.
0 No error.
1 Response CRC error occurred.
Read CRC Error. This indicates a transmission error occurred on the DAT line during a card read. Software
should retry the transmission. Writing a 1 to this bit clears the bit.
0 No error.
1 CRC read error occurred.
Write CRC Error. This indicates a transmission error occurred on the DAT line during a card write operation.
Software needs to check the SDHC_STATUS[WR_CRC_ERR_CODE] bitfield for more information about the
CRC error. Writing a 1 to this bit clears this bit.
0 No error.
1 CRC write error occurred.
No transmission error, CRC status is 010 (positive).
Transmission error, CRC status is 110 (negative).
No CRC response.
Reserved.
software needs to check the SDHC_STATUS[READ_CRC_ERR] and
SDHC_STATUS[TIME_OUT_READ] bits to determine if an error has occurred.
Table 28-5. SDHC_STATUS field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
Freescale Semiconductor