MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 866

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32-38
Address: Base + 0x184 (USB_PORTSC0, USB0)
Reset
Reset
WKOC
PHCD
PSPD
PFSC
Field
PTS
W
W
R
R
Base + 0x188 (USB_PORTSC1, USB1)
Base + 184h + (4 × (Port Number –1))
USB1/USB2
16
1
0
0
PTS
PIC
Port Transceiver Select. This register bit controls which parallel transceiver interface is selected.
10 ULPI parallel interface
All other values are reserved.
Port Speed. This read-only register field indicates the speed at which the port is operating.
This bit is not defined in the EHCI specification.
00 Full-speed
01 Low-speed
10 High-speed
11 Undefined
Port Force Full-speed Connect. This bit disables the chirp sequence that allows the port to identify itself as an
HS port. This is useful for testing FS configurations with an HS host, hub, or device.
0 Allow the port to identify itself as High Speed.
1 Force the port to only connect at Full-speed.
This bit is not defined in the EHCI specification.
This bit is for debugging purposes.
PHY Low Power Suspend. This bit is not defined in the EHCI specification.
In host mode, the PHY can be put into low power suspend when the downstream device has been put into
suspend mode or when no downstream device is connected. Low-power suspend is completely under the
control of software.
For the OTG module in device mode, the PHY can be put into low power suspend when the device is not
running (USB_USBCMD Run/Stop = 0) or suspend signaling is detected on the USB. Low-power suspend is
cleared automatically when the resume signaling has been detected or when forcing port resume.
0 Normal PHY operation.
1 Signal the PHY to enter low power suspend mode
Reading this bit indicates the status of the PHY.
Wake On Over-Current Enable. Writing this bit to 1 enables the port to be sensitive to over-current conditions
as wake-up events.
This field is 0 if Port Power (PP) is 0.
This bit is (OTG/host mode only) for use by an external power control circuit.
17
0
0
1
Figure 32-31. Port Status and Control n (USB_PORTSCn) Register
PO
18
0
0
2
0
PP
19
0
0
3
0
Table 32-32. USB_PORTSCn field descriptions
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
1
0
PSPD
LS
21
1
0
5
HSP
22
0
0
0
6
PFSC PHCD WKOC WKDS WKCN
PR
23
0
0
7
Description
SUSP FPR
24
8
0
0
25
9
0
0
OCC OCA
w1c
10
26
0
0
11
27
0
0
PEC
w1c
12
28
0
0
Freescale Semiconductor
Access: User read/write
PE
13
29
0
0
PTC
CSC
w1c
14
30
0
0
CCS
15
31
0
0