MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 782

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Secure Digital Host Controller (SDHC)
28.3.2.4
The SDHC Command and Data Control (SDHC_CMD_DAT_CONT) register allows specifying the
format of data and response, and controls the Read/Wait cycle. After configuring this register, enabling the
MMC_SD_CLK causes the command and argument configured in the Command Number (SDHC_CMD)
register and the Command Argument (SDHC_ARG) register to be sent out to the card.
Figure 28-5
28-10
CLK_DIVIDER Clock Divider. Specifies the divider value to generate CLK_DIV from input clock SDHC_CLK.
PRESCALER
CLK_
Field
shows the SDHC_CMD_DAT_CONT register and
SDHC Command and Data Control (SDHC_CMD_DAT_CONT) Register
Maximum frequency of MMC_SD_CLK is SDHC_CLK/1 when
CLK_DIVIDER and CLK_PRESCALER are set to 0x0.
Clock Prescaler. Specifies divider value to generate CLK_20M from CLK_DIV.
0x000 CLK_20M is CLK_DIV
0x001 CLK_20M is CLK_DIV/2
0x002 CLK_20M is CLK_DIV/4
0x004 CLK_20M is CLK_DIV/8
0x008 CLK_20M is CLK_DIV/16
0x010 CLK_20M is CLK_DIV/32
0x020 CLK_20M is CLK_DIV/64
0x040 CLK_20M is CLK_DIV/128
0x080 CLK_20M is CLK_DIV/256
0x100 CLK_20M is CLK_DIV/512
0x200 CLK_20M is CLK_DIV/1024
0x400 CLK_20M is CLK_DIV/2048
0x800 CLK_20M is CLK_DIV/4096
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC CLK_DIV is SDHC_CLK /13
0xD CLK_DIV is SDHC_CLK /14
0xE
0xF
CLK_DIV is SDHC_CLK
CLK_DIV is SDHC_CLK/2
CLK_DIV is SDHC_CLK/3
CLK_DIV is SDHC_CLK /4
CLK_DIV is SDHC_CLK /5
CLK_DIV is SDHC_CLK /6
CLK_DIV is SDHC_CLK /7
CLK_DIV is SDHC_CLK /8
CLK_DIV is SDHC_CLK /9
CLK_DIV is SDHC_CLK /10
CLK_DIV is SDHC_CLK /11
CLK_DIV is SDHC_CLK /12
CLK_DIV is SDHC_CLK /15
CLK_DIV is SDHC_CLK /16
Table 28-6. SDHC_CLK_RATE field descriptions
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
Description
Table 28-7
describes the bit fields.
Freescale Semiconductor