MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 923

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Alternatively, a host controller implementation is allowed to traverse the entire asynchronous schedule list
(for example, observed the head of the queue twice) before setting the advance on async status bit.
Software may re-use the memory associated with the removed queue heads after it observes the interrupt
on async advance status bit is set, following assertion of the doorbell. Software should acknowledge the
interrupt on async advance status as indicated in the USB_USBSTS register, before using the doorbell
handshake again.
32.6.7.3
EHCI uses two bits to detect when the asynchronous schedule is empty. The queue head data structure (see
Figure
head of the reclaim list. Host controller also keeps a 1-bit flag in the USB_USBSTS register (reclamation)
that is cleared when the host controller observes a queue head with the H-bit set. The reclamation flag in
the status register is set when any USB transaction from the asynchronous schedule is executed or when
the asynchronous schedule starts, see
If the controller ever encounters an H-bit of one and a reclamation bit of zero, the controller simply stops
traversal of the asynchronous schedule.
An example illustrating the H-bit in a schedule is shown in
Freescale Semiconductor
32-49) defines an H-bit in the queue head that allows software to mark a queue head as being the
HC State
Empty Asynchronous Schedule Detection
A
A
Memory State
Before Unlink
B
Async-Advance Doorbell = 0
USB_USBCMD Interrupt on
Figure 32-57. Generic Queue Head Unlink Scenario
MPC5125 Microcontroller Reference Manual, Rev. 2
C
HC State
D
Section 32.6.7.5, “Asynchronous Schedule Traversal: Start Event.”
A
USB_USBSTS Interrupt on Async-Advance = 1
D
Async-Advance Doorbell = 0
USB_USBCMD Interrupt on
After Doorbell
Memory State
B
C
HC State
Figure
USB_USBSTS Interrupt on Async-Advance = 0
After Unlink (B, C) and at Doorbell
A
A
D
32-58.
Async-Advance Doorbell = 1
Universal Serial Bus Interface with On-The-Go
USB_USBCMD Interrupt on
Memory State
B
C
D
32-95