MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 680

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Serial Controller (PSC)
25.2
General features:
PSC universal asynchronous receiver/transmitter (UART) mode:
PSC codec mode:
AC97 mode:
25-2
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Each channel is programmable to normal (full-duplex), automatic echo, local loop-back, or remote
loop-back mode
Automatic wake-up mode for multidrop applications
Six maskable interrupt conditions
Each is clocked by an internal clock source (IPB clock), eliminating the need for an external crystal
Full-duplex asynchronous receiver/transmitter channel
Programmable data format:
— 5 to 8 data bits plus parity
— Odd, even, no parity, or force parity
— 1, 1.5, or 2 stop bits
Parity, framing, and overrun error detection
False-start bit detection
Line-break detection and generation
Detection of breaks originating in the middle of a character
Start/end break interrupt/status
Programmable to interface to an 8-, 12-, 16-, 20-, 24-, or 32-bit codec for soft modem support
Supports master mode, driving clock, and FrameSync signals
Supports slave mode, receiving clock, and the FrameSync from the external codec
Supports multichannel mode, with 3 data lines in codec mode
Supports full duplex Serial Peripheral Interface (SPI) interface
Supports I
No parity error, framing error, or line break detection in codec mode
Ability to generate a master clock (MCLK) for an external codec device, independent from the
mode (master or slave)
Programmable width of the FrameSync signal
FrameSync and bit clock frequencies are independently programmable
FrameSync and bit clock polarity are programmable
Supports AC97 mode, only the data slots must be available, the control slot data are generated by
the PSC
Supports AC97 wake-up and power-down modes
Features
2
S interface
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor