MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 693

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.4.1.7
Writing to this register places data directly into the TX shift register. This access bypasses the data in the
TX FIFO. Use the data register in the TX FIFO to provide the TX data.
Freescale Semiconductor
Address: Base + 0x14
Address: Base + 0x14
Reset
Reset
Reset
Reset
Field
SOF
RB
W
W
W
W
20
R
R
R
R
16
16
0
0
0
0
0
0
Tx Buffer Register (TB)
AC97 (0:19). Received data. AC97 data must be read one complete sample at a time, where all samples
except time slot #0 are 20 bits. Time slot #0 data is in bits 0:15. The bits [21:31] are reserved at this mode.
UART/Codec8 (0:31). Received data. For these modes, data can be read 1, 2, or 4 bytes at a time. For 1
byte at a time, all bytes must be read from bits 0:7. For 2 bytes at a time, data must be read from bits 0:15.
Lower-bit data was received before upper-bit data.
Codec16 (0:31). Received data. For these modes, data can be read 2 or 4 bytes at a time. For 2 bytes at a
time, data must be read from bits 0:15. Lower-bit data was received before upper-bit data.
Codec24 (0:23). Received data. For these modes, data must be read 4 bytes at a time. The lower 24 bits
contain the received data word.
Codec32 (0:31). Received data. For these modes, data must be read 4 bytes at a time.
SOF (bit 20) is 1 in the first sample of a new frame, and contains the Start Of Frame indicator.
0 RB[0:19] is not the first sample in the frame.
1 RB[0:19] is the first sample in a new frame. The number 0 slot is called the TAG slot.
RB[16:19]
17
17
0
0
0
0
1
1
18
18
0
0
0
0
2
2
Figure 25-15. Rx Buffer Register for Codec24 Mode (RB)
Figure 25-14. Rx Buffer Register for AC97 Mode (RB)
RB[16:23]
19
19
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
20
4
0
0
0
4
0
0
Table 25-11. RB field descriptions
21
21
0
0
0
0
0
5
5
22
22
0
0
0
0
0
6
6
Used by Tx Buffer
Used by Tx Buffer
Used by Tx Buffer
Used by Tx Buffer
23
23
RB[0:15]
0
0
0
RB[0:15]
0
0
7
7
Description
24
24
8
0
0
0
8
0
0
0
25
25
9
0
0
0
9
0
0
0
10
26
10
26
0
0
0
0
0
0
Programmable Serial Controller (PSC)
11
27
11
27
0
0
0
0
0
0
12
28
12
28
0
0
0
0
0
0
Access: User read-only
Access: User read-only
13
29
13
29
0
0
0
0
0
0
14
30
14
30
0
0
0
0
0
0
25-15
15
31
15
31
0
0
0
0
0
0