MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 315

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
FIFO OV PENDING
FIFO UV PENDING
FIFO OV CLEAR
FIFO UV CLEAR
FIFO OV EN
FIFO UV EN
Field
{rdly[3:0],half_dqs_dly,quart_dqs_dly}
DQS Enable (Internal)
Table 11-2. DDR_SYS_CONFIG field descriptions (continued)
These bits control the interrupt generation by the DRAM controller. The DRAM controller has two
interrupts: FIFO OV pending and FIFO UV pending. These interrupts are set on overflow or
underflow of the FIFO in the read block. When a read command is sent to the DRAM, it is entered
into a FIFO. The DRAM is expected to answer by sending back the read data with some up and down
edges on the DQS lines (the DQS strobes) used to clock the data. The DRAM controller clocks the
read data with the DQS strobes supplied by the DRAM and retrieves the read command from the
FIFO after receiving the correct number of read strobes. When the read data strobes returned by the
DRAM do not match the expectations of the controller, the FIFO may underflow (if too many DQS
strobes are coming back from the DRAM) or overflow (if not enough DQS strobes are coming back).
These underflows and overflows are basically the result of problems with the DRAM interface or
incorrect parameter settings in the controller or the DRAM. Care has been taken during the design
of the DRAM controller not to enter a hang-up state when this occurs. However, read data is corrupt
and CPU is informed via the FIFO overflow and FIFO underflow interrupts. The issue is also
discussed in
• FIFO_OV_PENDING and FIFO_UV_PENDING signal to the CPU if an overflow or underflow
• FIFO_OV_EN and FIFO_UV_EN bits are interrupt enable bits. If the pending + enable bit is set
• FIFO_OV_CLEAR and FIFO_UV_CLEAR are clear bits. Writing a 1 to either of these clears the
interrupt is pending
at the same time, the interrupt is sent to the e300 CPU.
pending interrupt.
DRAM Command
DRAM Clock
MPC5125 Microcontroller Reference Manual, Rev. 2
DQS (in)
1000 0 0
1000 0 1
1000 1 0
1000 1 1
0100 0 0
0100 0 1
0100 1 0
0100 1 1
0010 0 0
0010 0 1
Section 11.4.7, “Bus Interface.”
Table 11-3. Programming t
Figure 11-3. t
Read
DQSEN
Description
tDQSEN
fall in preamble of DQS (in)
DQS enable L-to-H must
t
DQSEN
DQSEN
(CSB Clock Periods)
0.75
1.25
1.75
2.25
2.75
0.5
1.0
1.5
2.0
2.5
DRAM Controller
11-7