MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 421

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

the ICT field of the GPT_MODE register, occurs. The value of the up/down counter can be obtained by
reading the COUNT field of the GPT_COUNTER register for the particular timer channel.
An interrupt is generated, if enabled, when the UP Down Counter overflows.
The UP DOWN Counter cannot be modified by software.
15.3.1.3
When using the UP DOWN submode, the up/down counter and internal counter are active. A pair of GPT
channels must be used to implement this mode. Timer Channel 0 is paired with Timer Channel 1, Timer
Channel 2 is paired with Timer Channel 3, Timer Channel 4 is paired with Timer Channel 5 and Timer
Channel 6 is paired with Timer Channel 7. The ICM field of the GPT_MODE register for both timer
channels must be set to 0b10.
The ICT field in the GPT_MODE register for both channels must be programmed to detect the desired
transitions. After a pair of channels is properly programmed, the up/down counter of one channel
increments each time an Input Capture Event occurs on this channel of the pair and decrements by 1 when
an Input Capture Event occurs on the other channel of the pair. That is, for the pair of channels consisting
of Timer Channel 0 and Timer Channel 1, the up/down counter associated with Timer Channel 0
increments if an Input Capture event occurs on Timer Channel 0 and decrements if an Input Capture event
occurs on Timer Channel 1.
An interrupt is generated, if enabled, when the up/down counter either underflows or overflows.
15.3.1.4
When using the ROTARY submode, both the up/down counter and internal counter are active. A pair of
GPT channels must be used to implement this mode. Timer Channel 0 is paired with Timer Channel 1,
Timer Channel 2 is paired with Timer Channel 3, Timer Channel 4 is paired with Timer Channel 5 and
Timer Channel 6 is paired with Timer Channel 7. The ICM field of the GPT_MODE register for both timer
channels must be set to 0b11.
The ICT field in the GPT_MODE register for one channel of the pair must be programmed to detect the
desired transitions. After a pair of channels is properly programmed, the up/down counter increments each
time an Input Capture Event occurs on one channel of the pair if the logic level on the input of the other
Channel of the pair is a logic 0. The up/down counter decrements each time an Input Capture Event occurs
on one channel of the pair if the logic level on the input of the other Channel of the pair is a logic 1.
For instance, if Timer Channel 0 is programmed to recognize positive transitions, the up/down counter
associated with Timer Channel 0 increments each time a positive transition is detected on Timer Channel 0
if the logic level on Timer Channel 1 is a logic 0. The up/down counter associated with Timer Channel 0
decrements each time a positive transition is detected on Timer Channel 0 if the logic level on Timer
Channel 1 is a logic 1.
15.3.2
Freescale Semiconductor
Changing Sub-Modes
UP DOWN Mode
Rotary Mode
MPC5125 Microcontroller Reference Manual, Rev. 2
General Purpose Timers (GPT)
15-11