MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 512

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Inter-Integrated Circuit (I
19.3.1.5
1
19.3.1.6
19-20
Address: Base + 0x10 (I2C_MDR1)
Address: Base + 0x60
When I
is written to it. The read out data of this register is updated only when the received data from the external device is changed,
otherwise it remains unchanged.
Reset
Reset
Reset
Reset
D[7:0]
Field
W
W
W
W
R
R
R
R
2
C is disabled (bitfield “EN” in I
Base + 0x30 (I2C_MDR2)
Base + 0x50 (I2C_MDR3)
1
D7
16
16
0
0
0
0
0
0
0
0
0
I
I
2
2
Master Transmit Mode. When data is written to this register, a data transfer is initiated. The most significant
bit is sent first.
Note: In this mode, the first data byte written to DR. Assertion of STA is used for the address transfer and
In Master Receive Mode, reading this register initiates next byte data receiving.
In Slave Mode, the same functions are available after an address match occurs.
C Data I/O Register (I2C_MDRn)
C Interrupt Control Register (I2C_ICR)
D6
17
17
0
0
0
0
0
0
0
1
1
2
C)
should be comprised of the calling address (in position D[7]:D[1]) concatenated with the required R/W
bit (in position D0).
BNBE
D5
18
18
0
0
0
3
0
0
0
2
2
Figure 19-14. I
IE3
D4
19
19
0
0
0
1
0
0
3
3
Figure 19-13. I
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 19-9. I2C_MDRn field descriptions
2
BNBE
C control register is equal to zero), this register always reads back zero, whatever value
D3
20
20
4
0
0
0
4
2
0
0
0
IE2
2
D2
21
21
0
0
0
1
0
0
5
5
C Interrupt Control Register (I2C_ICR)
2
C Data I/O Register (I2C_MDRn)
BNBE
D1
22
22
0
0
0
1
0
0
0
6
6
IE1
D0
23
23
0
0
0
1
0
0
7
7
Description
24
24
8
0
0
0
0
8
0
0
0
0
25
25
9
0
0
0
0
9
0
0
0
0
10
26
10
26
0
0
0
0
0
0
0
0
11
27
11
27
0
0
0
0
0
0
0
0
12
28
12
28
0
0
0
0
0
0
0
0
Freescale Semiconductor
Access: User read/write
Access: User read/write
13
29
13
29
0
0
0
0
0
0
0
0
14
30
14
30
0
0
0
0
0
0
0
0
15
31
15
31
0
0
0
0
0
0
0
0