MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 649

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

There are two interrupts to flag the end of a command execution:
Use the CMD_DONE_IRQ interrupt if commands are sent back-to-back to the flash. It gives an indication
when a new command can be dispatched. The done interrupt is given before the flash data is corrected and
resident in memory, because operation of the ECC engine and DMA engine is pipelined.
When the CMD_DONE_IRQ interrupt is used to track command completion, the software may also
monitor the ECC_BUSY, DMA_BUSY, ECC_BUFF_NO, and DMA_BUFF_NO bitfields. The
ECC_BUSY bitfield indicates that the ECC block is still busy, and gives the number of the buffer on which
the ECC block is working in the ECC_BUFF_NO bitfield. The DMA_BUSY bitfield indicates that the
DMA block is still busy, and gives the number of the the buffer on which the DMA block is working in
the DMA_BUFF_NO bitfuield.
Use the IDLE_IRQ interrupt if you want to use the data produced in the next process. The IDLE_IRQ
interrupt indicates that all command processing has terminated, and the relevant data is now available
either in memory or in the NFC SRAM buffer. When using back-to-back reads to the flash, use of the
IDLE_IRQ interrupt means the NFC does not operate at its maximum transfer speed, as ECC and DMA
are now done in foreground.
When using the CMD_DONE_IRQ interrupt, transfer completion for write pages can be assumed when
the CMD_DONE_IRQ interrupt is received. When CMD_DONE_IRQ is received for read pages, the data
may still be in flight in the DMA or the ECC. To check this, the CPU should remember the buffer number
(xxx_BUFNO bitfield) associated with the command, and wait until the DMA and ECC are either idle, or
are both busy on a different buffer number. (ECC buffer number and DMA buffer number fields do not
match xxx_BUFNO specified with command.) Checking can be done on any CMD_DONE_IRQ interrupt,
or by polling the register.
23.8
The NFC executes commands on an external, or bank of external NAND Flash chips. The commands
supported include read, program, reset, erase, status read, read ID, etc.
The NFC block has DMA engine and built-in ECC logic. For each read or write, ECC calculations are
performed on-the-fly. Two DMA channels are organized for each read or write: One for the main area, and
one for the spare area. It is possible to disable the second DMA channel, and transfer main and spare data
with just the first DMA channel.
Freescale Semiconductor
RESIDUE_BUFF_NO Residue buffer number. Buffer number corresponding with the current residue block task.
CMD_DONE_CLEAR Clear bit for CMD_DONE_IRQ. Writing ‘1’ to this bit clears CMD_DONE_IRQ.
DMA_BUFF_NO
ECC_BUFF_NO
•
•
IDLE_CLEAR
The done interrupt CMD_DONE_IRQ
The cidle (command idle) interrupt IDLE_IRQ
Field
Functional Description
Clear bit for IDLE_IRQ. Writing ‘1’ to this bit will clear IDLE_IRQ.
ECC buffer number. Buffer number corresponding with the current ECC task.
DMA buffer number. Buffer number corresponding with the current DMA task.
Table 23-18. IRQ_STATUS field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
NAND Flash Controller (NFC)
23-19