MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 953

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

If test A is non-zero, Test B indicates a match event, Test C indicates the previous complete-split was
appropriately executed and Test D evaluates to a NOT TRUE condition, the host controller executes a
complete-split transaction. When the host controller commits to executing the complete-split transaction,
it updates QH[C-prog-mask] by bit-ORing with cMicroFrameBit. On completion of the complete-split
transaction, the host controller records the result of the transaction in the queue head and sets
QH[FrameTag] to the expected H-Frame number. The effect to the state of the queue head and thus the
state of the transfer depends on the response by the transaction translator to the complete-split transaction.
The following responses have the effects (any responses that result in decrementing of the Cerr result in
the queue head being halted by the host controller if the result of the decrement is zero):
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NYET (and Last). On each NYET response, the host controller checks to determine whether this
is the last complete-split for this split transaction. Last is defined in this context as the condition
where all of the scheduled complete-splits have been executed. If it is the last complete-split (with
a NYET response), the transfer state of the queue head is not advanced (never received any data)
and this state exited. The transaction translator must have responded to all the complete-splits with
NYETs, meaning the start-split issued by the host controller was not received. The start-split
should be retried at the next poll period.
The test for whether this is the last complete split can be performed by XOR QH[C-mask] with
QH[C-prog-mask]. If the result is all zeros, all complete-splits have been executed. When this
condition occurs, the XactErr status bit is set and the Cerr field is decremented.
NYET (and not Last). See above description for testing for last. The complete-split transaction
received a NYET response from the transaction translator. Do not update any transfer state (except
for C-prog-mask and FrameTag) and stay in this state. The host controller must not adjust Cerr on
this response.
Transaction Error (XactErr). Timeout, data CRC failure, etc. The Cerr field is decremented and the
XactErr bit in the Status field is set. The complete split transaction is immediately retried (if Cerr
is non-zero).If there is not enough time in the micro-frame to complete the retry and the endpoint
is an IN or Cerr is decremented to a zero from a one, the queue is halted. If there is not enough time
in the micro-frame to complete the retry and the endpoint is an OUT and Cerr is not zero, this state
is exited (return to Do Start Split). This results in a retry of the entire OUT split transaction at the
next poll period. Refer to Chapter 11 Hubs (specifically the section on full- and low-speed
interrupts) in the USB Specification Revision 2.0 for detailed requirements on why these errors
must be immediately retried.
ACK. This can only occur if the target endpoint is an OUT. The target endpoint ACKed the data
and this response is a propagation of the endpoint ACK to the host controller. The host controller
must advance the state of the transfer. The current offset field is incremented by maximum packet
length or bytes to transfer, whichever is less. The bytes to transfer field is decremented by the same
amount, and the data toggle bit (dt) is toggled. The host controller then exits this state for this queue
head. The host controller must reload Cerr with maximum value on this response. Advancing the
transfer state may cause other process events such as retirement of the qTD and advancement of
the queue.
MDATA. This response occurs only for an IN endpoint. The transaction translator responded with
zero or more bytes of data and an MDATA PID. The incremental number of bytes received is
accumulated in QH[S-bytes]. The host controller must not adjust Cerr on this response.
MPC5125 Microcontroller Reference Manual, Rev. 2
Universal Serial Bus Interface with On-The-Go
32-125