MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 162

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Byte Data Link Controller (BDLC)
The minimum and maximum symbol limits shown in the following sections
BREAK
through
Invalid Passive Bit
If the passive to active transition beginning the next data bit or symbol occurs between the active to passive
transition beginning the current data bit or symbol and T
Figure
6-26
Note: The receiver symbol timing boundaries are subject to an uncertainty of 1 t
Note: The receiver symbol timing boundaries are subject to an uncertainty of 1 t
Number
Number
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
6-13(1).
Table
Symbol) and figures
6-21.
Table 6-20. BDLC Receiver VPW 4X Symbol Timing for Integer Frequencies
Table 6-21. BDLC Receiver VPW 4X Symbol Timing for Binary Frequencies
Inter-Frame Separator (IFS)
Inter-Frame Separator (IFS)
Break Signal (BREAK)
Break Signal (BREAK)
Start of Frame (SOF)
Start of Frame (SOF)
End of Frame (EOF)
End of Frame (EOF)
End of Data (EOD)
End of Data (EOD)
Passive Logic 0
Passive Logic 1
Passive Logic 0
Passive Logic 1
Characteristic
Characteristic
Active Logic 0
Active Logic 1
Active Logic 0
Active Logic 1
MPC5125 Microcontroller Reference Manual, Rev. 2
(Figure 6-13
through
Symbol
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
rvp1
rvp2
rvp3
rvp1
rvp2
rvp3
rva1
rva2
rva3
rva1
rva2
rva3
Figure
rv4
rv5
rv6
rv4
rv5
rv6
rvp1(Min)
6-16) refer to the values listed in
Min
Min
24
24
41
41
60
75
60
26
26
43
43
63
79
63
8
8
9
9
, the current bit would be invalid. See
bdlc
bdlc
due to sampling considerations.
due to sampling considerations.
Typ
Typ
16
32
32
16
50
50
70
17
34
34
17
53
53
74
—
—
—
—
(Invalid Passive Bit–Valid
Freescale Semiconductor
Max
Max
23
40
40
23
59
59
74
25
42
42
25
62
62
78
—
—
—
—
Table 6-16
Unit
Unit
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
bdlc
bdlc
bdlc
bdlc
bdlc
bdlc
bdlc
bdlc
bdlc
bdlc
bdlc
bdlc
bdlc
bdlc
bdlc
bdlc
bdlc
bdlc