MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 746

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PSC Centralized FIFO Controller (FIFOC)
26.2.1.9
26.2.1.10 FIFOC Command Register (FIFOC_CMD)
26-12
CLOCK_GATE_
Address: Base + 0xBC (PSCn_TX_SIZE)
Address: FIFOC Base + 0x00
Reset
Reset
Reset
Reset
Field
DATA
Field
EN
W
W
W
W
R
R
R
R
Base + 0xFC (PSCn_RX_SIZE)
16
16
0
0
0
0
0
0
0
0
Data Register (DATA)
Data Register. Write access to this register writes the data to the FIFO. Read access from this register reads
the data from the FIFO.
Dynamic Clock Gating Enabled
0 Dynamic clock gating is disabled
1 Dynamic clock gating is enabled, the FIFO gates off the internal clock if no access is available. This
17
17
0
0
0
0
0
0
1
1
behavior increases the number of IP bus wait cycles by one.
18
18
0
0
0
0
0
0
2
2
Figure 26-11. FIFOC Command Register (FIFOC_CMD)
19
19
0
0
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 26-13. FIFOC_CMD field descriptions
20
Table 26-12. DATA field descriptions
20
4
0
0
4
0
0
0
0
Figure 26-10. Data Register (DATA)
21
21
0
0
0
0
0
0
5
5
22
22
0
0
0
0
0
0
6
6
23
23
0
0
0
0
0
0
7
7
DATA
DATA
Description
Description
24
24
8
0
0
8
0
0
0
0
25
25
9
0
0
9
0
0
0
0
10
26
10
26
0
0
0
0
0
0
11
27
11
27
0
0
0
0
0
0
12
28
12
28
0
0
0
0
0
0
Freescale Semiconductor
Access: User read/write
Access: User read/write
13
29
13
29
0
0
0
0
0
0
14
30
14
30
0
0
0
0
0
0
CLOC
K_GA
TE_E
15
31
15
31
N
0
0
0
0
0