MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 848

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32-20
FS[1:0]
Field
ASE
PSE
RST
IAA
Interrupt on Async Advance Doorbell. Software uses this bit as a doorbell to tell the controller to issue an
interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the
doorbell.
When the controller has evicted all appropriate cached schedule states, it sets the interrupt on async advance
status bit in the USB_USBSTS register. If the interrupt on sync advance enable bit in the USB_USBINTR
register is 1, the host controller asserts an interrupt at the next interrupt threshold.
The controller sets this bit to 0 after it has set the interrupt on sync advance status bit in the USB_USBSTS
register to 1. Software should not write a 1 to this bit when the asynchronous schedule is inactive. Doing so
yields undefined results.
This bit is only used in host mode. Writing a 1 to this bit when the OTG module is in device mode has undefined
results.
Asynchronous Schedule Enable. This bit controls whether the controller skips processing the asynchronous
schedule. Only used in host mode.
0 Do not process the asynchronous schedule.
1 Use the USB_ASYNCLISTADDR register to access the asynchronous schedule.
Periodic Schedule Enable. This bit controls whether the controller skips processing the periodic schedule.
Only used in host mode.
0 Do not process the periodic schedule.
1 Use the USB_PERIODICLISTBASE register to access the periodic schedule.
Frame List Size. With bit 15, these bits make the FS[2:0] field. This field is read/write only if the programmable
frame list flag (PFL bit) in the USB_HCCPARAMS register is set to 1. This field specifies the size of the frame
list that controls which bits in the frame index register should be used for the frame list current index. Used
only in host mode. Values below 256 elements are not defined in the EHCI specification.
Controller Reset. Software uses this bit to reset the controller. This bit is set to 0 by the controller when the
reset process is complete. Software cannot terminate the reset process early by writing a 0 to this register.
Host Mode:
When software writes a 1 to this bit, the Host Controller resets its internal pipelines, timers, counters, state
machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated.
A USB reset is not driven on downstream ports. Software should not set this bit to a 1 when the HCHalted bit
in the USB_USBSTS register 0. Attempting to reset an actively running host controller results in undefined
behavior.
Device Mode:
When software writes a 1 to this bit, the OTG controller resets its internal pipelines, timers, counters, state
machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated.
Writing a 1 to this bit in device mode is not recommended.
Table 32-16. USB_USBCMD field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
FS2 FS1 FS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Description
1024 elements (4096 bytes)
512 elements (2048 bytes)
256 elements (1024 bytes)
128 elements (512 bytes)
64 elements (256 bytes)
32 elements (128 bytes)
16 elements (64 bytes)
8 elements (32 bytes)
Descriptions
Freescale Semiconductor