MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 213

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.3
The following sections describe arbiter functionality: arbitration policy and bus error detection.
8.3.1
The arbitration process involves the masters and the arbiter. The masters arbitrate for the privilege of
owning the address tenure. For the data tenure, the CSB arbiter uses the same order of transactions as
address tenures.
involved in the address bus arbitration.
A master has to acquire the address bus ownership before it starts any transaction. The master asserts its
own bus request signal along with the arbitration attribute signals REPEAT and PRIORITY[0:1]. The
arbiter later asserts the corresponding address bus grant signal to the requesting master depending on the
system states and arbitration scheme. See
PRIORITY[0:1],”
the master can start the address tenure.
8.3.1.1
When a master asserts its bus request to acquire the address bus ownership, it can drive its PRIORITY[0:1]
signals to indicate request priority. The master would be served sooner because of its higher priority level.
The arbiter takes this extra information into consideration to yield better service for a higher priority
request than a lower priority request. Therefore, the arbiter operates according to the following priority
based arbitration scheme:
Freescale Semiconductor
1. For every priority level fair arbitration scheme is used (a simple Round Robin scheme).
Functional Description
Arbitration Policy
Address Bus Arbitration With PRIORITY[0:1]
Figure 8-10
for details information on arbitration scheme. When the address bus grant is received,
Master N
Master 1
Master 2
shows the interface signals between the CSB arbiter and masters that are
•
•
•
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 8-10. Address Bus Arbitration
Section 8.3.1.1, “Address Bus Arbitration With
PRIORITY[0:1]
PRIORITY[0:1]
PRIORITY[0:1]
REPEAT
REPEAT
REPEAT
BR
BG
BR
BG
BR
BG
Arbiter
CSB Arbiter and Bus Monitor
8-13